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公开(公告)号：US06528405B1
公开(公告)日：2003-03-04
申请号：US09506844
申请日：2000-02-18
IPC分类号： H01L2128
CPC分类号： H01L29/66462 , H01L21/28587 , H01L29/7784
摘要： An enhancement mode RF device and method of fabrication includes a stack of compound semiconductor layers, including a central layer defining a device channel, a doped cap layer, and a buffer epitaxially grown on a substrate. Source and drain implant areas, extending at least into the buffer, are formed to define an implant free area in the device channel between the source and drain. Source and drain metal contacts are positioned on an upper surface of the central layer. Several layers of insulation and dielectric are positioned over the device and a gate opening is formed and filled with gate metal. During epitaxial growth, the doped cap layer is tailored with a thickness and a doping to optimize channel performance including gate-drain breakdown voltage and channel resistance.
摘要翻译： 增强型RF器件和制造方法包括：化合物半导体层的堆叠，包括限定器件沟道的中心层，掺杂的覆盖层和在衬底上外延生长的缓冲层。 形成至少延伸到缓冲器中的源极和漏极注入区域，以在源极和漏极之间的器件沟道中限定无植入区域。 源极和漏极金属触点位于中心层的上表面上。 绝缘和电介质的几层位于器件上方，并形成栅极开口并填充栅极金属。 在外延生长期间，掺杂的覆盖层是通过厚度和掺杂来调整的，以优化沟道性能，包括栅 - 漏击穿电压和沟道电阻。
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公开(公告)号：US06893947B2
公开(公告)日：2005-05-17
申请号：US10179769
申请日：2002-06-25
申请人： Marino J. Martinez , Ernest Schirmann , Olin L. Hartin , Colby G. Rampley , Mariam G. Sadaka , Charles E. Weitzel , Julio Costa
发明人： Marino J. Martinez , Ernest Schirmann , Olin L. Hartin , Colby G. Rampley , Mariam G. Sadaka , Charles E. Weitzel , Julio Costa
IPC分类号： H01L21/285 , H01L21/337 , H01L29/80 , H01L21/22
CPC分类号： H01L29/66924 , H01L21/28587 , H01L29/802
摘要： A method for fabricating an RF enhancement mode FET (30) having improved gate properties is provided. The method comprises the steps of providing (131) a substrate (31) having a stack of semiconductor layers (32-35) formed thereon, the stack including a cap layer (35) and a central layer (33) defining a device channel, forming (103) a photoresist pattern (58) over the cap layer, thereby defining a masked region and an unmasked region, and, in any order, (a) creating (105) an implant region (36, 37) in the unmasked region, and (b) removing (107) the cap layer from the unmasked region. By forming the implant region and cap region with no overlap, a device with low current leakage may be achieved.
摘要翻译： 提供了一种制造具有改进的栅极特性的RF增强型FET（30）的方法。 该方法包括以下步骤：提供（131）具有形成在其上的半导体层（32-35）的堆叠的衬底（31），所述堆叠包括限定器件沟道的覆盖层（35）和中心层（33） 在所述盖层上形成（103）光致抗蚀剂图案（58），由此限定掩蔽区域和未掩蔽区域，并且以任何顺序，（a）在所述未掩蔽区域中产生（105）植入区域（36,37） ，和（b）从未掩蔽区域移除（107）盖层。 通过不重叠地形成注入区域和盖子区域，可以实现具有低电流泄漏的装置。
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公开(公告)号：US5945694A
公开(公告)日：1999-08-31
申请号：US792606
申请日：1997-01-31
IPC分类号： H01L21/338 , H01L29/04 , H01L29/812 , H01L31/0328 , H01L31/0336 , H01L31/072 , H01L31/109
CPC分类号： H01L29/812 , H01L29/045
摘要： A semiconductor device (20) is formed on a compound semiconductor substrate (21). The semiconductor device (20) is oriented on the surface (40) of the compound semiconductor substrate (21) such that the physical forces that result from the thermal heating or cooling of the compound semiconductor substrate (21) are essentially equal. This orientation reduces the variability of the drain to source current of the semiconductor device (20) as the semiconductor device (20) is operated at different temperatures.
摘要翻译： 半导体器件（20）形成在化合物半导体衬底（21）上。 半导体器件（20）被定向在化合物半导体衬底（21）的表面（40）上，使得由化合物半导体衬底（21）的热加热或冷却产生的物理力基本相等。 当半导体器件（20）在不同温度下操作时，该取向降低了半导体器件（20）的漏极 - 源极电流的可变性。
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公开(公告)号：US06023086A
公开(公告)日：2000-02-08
申请号：US926078
申请日：1997-09-02
IPC分类号： H01L23/482 , H01L29/423 , H01L29/43 , H01L29/76
CPC分类号： H01L29/435 , H01L23/4824 , H01L29/42316 , H01L29/42372 , H01L2924/0002
摘要： A semiconductor device includes a transistor (30, 51) having a gate electrode (15, 52) wherein the gate electrode (15, 52) has a highly resistive portion (24, 25, 55). The highly resistive portion (24, 25, 55) is integrated into the gate electrode (15, 52) and is coupled to the gate electrode (15, 52) using a via-less contact method.
摘要翻译： 半导体器件包括具有栅电极（15,52）的晶体管（30,51），其中栅电极（15,52）具有高电阻部分（24,25,55）。 高电阻部分（24,25,55）集成到栅电极（15,52）中，并且使用无通孔接触方法耦合到栅电极（15,52）。
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公开(公告)号：US5742082A
公开(公告)日：1998-04-21
申请号：US753312
申请日：1996-11-22
IPC分类号： H01L21/338 , H01L29/10 , H01L29/812 , H01L29/80
CPC分类号： H01L29/66863 , H01L29/1075 , H01L29/8128
摘要： A stable FET including a substrate structure with a doped layer formed as a portion of the substrate structure and defining an electrically conductive shielding region adjacent a surface of the substrate structure. A channel region is positioned on the shielding region and includes a plurality of epitaxial layers grown on the surface of the substrate structure in overlying relationship to the doped layer. A drain and a source are positioned on the channel region in spaced relationship from each other with a gate positioned in overlying relationship on the channel region between the drain and source. An externally accessible electrical contact is connected to the shielding region and to the source region to provide a path for the removal of internally generated charges, such as holes.
摘要翻译： 一种稳定的FET，其包括具有掺杂层的衬底结构，所述掺杂层形成为所述衬底结构的一部分并且限定邻近所述衬底结构的表面的导电屏蔽区域。 通道区域位于屏蔽区域上，并且包括以与掺杂层相重叠的方式在衬底结构的表面上生长的多个外延层。 漏极和源极以彼此间隔开的关系定位在沟道区上，栅极位于漏极和源极之间的沟道区上的上限关系。 外部可接触的电触点连接到屏蔽区域和源极区域，以提供用于去除内部产生的电荷（例如孔）的路径。
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6.发明授权Semiconductor device using a barrier layer between the gate electrode and substrate and method therefor 有权在栅电极和衬底之间使用阻挡层的半导体器件及其方法公开(公告)号：US06521961B1
公开(公告)日：2003-02-18
申请号：US09560737
申请日：2000-04-28
IPC分类号： H01L3106
CPC分类号： H01L29/66871 , H01L21/28587 , H01L29/475 , H01L29/66462
摘要： An enhancement mode semiconductor device has a barrier layer disposed between the gate electrode of the device and the semiconductor substrate underlying the gate electrode. The barrier layer increases the Schottky barrier height of the gate electrode-barrier layer-substrate interface so that the portion of the substrate underlying the gate electrode operates in an enhancement mode. The barrier layer is particularly useful ill compound semiconductor field effect transistors, and preferred materials for the barrier layer include aluminum gallium arsenide and indium gallium arsenide.
摘要翻译： 增强型半导体器件具有设置在器件的栅极电极和栅极电极下方的半导体衬底之间的势垒层。 阻挡层增加了栅电极 - 阻挡层 - 衬底界面的肖特基势垒高度，使得栅电极下面的衬底的部分以增强模式工作。 阻挡层是特别有用的化合物半导体场效应晶体管，并且阻挡层的优选材料包括砷化铝镓和砷化铟镓。
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公开(公告)号：US5830774A
公开(公告)日：1998-11-03
申请号：US667013
申请日：1996-06-24
IPC分类号： H01L21/28 , H01L21/033 , H01L21/3205 , H01L21/44 , H01L21/441
CPC分类号： H01L21/0331
摘要： A method for forming a metal pattern on a substrate (11) includes forming a dielectric stack (14) on a major surface (12) of the substrate (11) and forming a mask (22) on the dielectric stack (14). The dielectric stack (14) includes an aluminum nitride layer (16) serving as an etch stop layer between two dielectric layers (15, 17). An opening is formed in the dielectric stack (14) via successive etching. The etching of the dielectric layer (15) between the aluminum nitride layer (16) and the substrate (11) undercuts the aluminum nitride layer (16). A metal layer (30) is deposited on the major surface through the opening via sputtering. The metal layer (30) on the major surface is distinctively separated from a metal layer (34) on the edge of the opening. The mask (22) is dissolved in a solvent, thereby lifting-off a metal layer (34) deposited on the mask (22).
摘要翻译： 在基板（11）上形成金属图案的方法包括在基板（11）的主表面（12）上形成介质叠层（14），并在介质叠层（14）上形成掩模（22）。 电介质堆叠（14）包括用作两个电介质层（15,17）之间的蚀刻停止层的氮化铝层（16）。 通过连续蚀刻在电介质堆叠（14）中形成开口。 在氮化铝层（16）和衬底（11）之间的介电层（15）的蚀刻使氮化铝层（16）下切。 通过溅射通过开口沉积在主表面上的金属层（30）。 主表面上的金属层（30）与开口边缘上的金属层（34）有明显的分离。 将掩模（22）溶解在溶剂中，从而剥离沉积在掩模（22）上的金属层（34）。
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公开(公告)号：US5719088A
公开(公告)日：1998-02-17
申请号：US556477
申请日：1995-11-13
申请人： Jenn-Hwa Huang , Mark Durlam , Marino J. Martinez , Ernie Schirmann , Saied N. Tehrani , William J. Ooms
发明人： Jenn-Hwa Huang , Mark Durlam , Marino J. Martinez , Ernie Schirmann , Saied N. Tehrani , William J. Ooms
IPC分类号： H01L21/285 , H01L21/311 , H01L21/335 , H01L23/485 , H01L21/44
CPC分类号： H01L29/66462 , H01L21/28587 , H01L21/31116 , H01L23/485 , H01L2924/0002
摘要： A method of fabricating semiconductor devices with a passivated surface includes providing a contact layer on a substrate so as to define an inter-electrode surface area. A first layer and an insulating layer, which are selectively etchable relative to each other and to the substrate and the contact layer, are deposited on the contact layer and the inter-electrode surface area. The insulating layer and the first layer are individually and selectively etched to define an electrode contact area and to expose the inter-electrode surface area. The exposed inter-electrode surface area is passivated, either subsequent to or during the etching of the first layer. A metal contact is formed in the electrode contact area in abutting engagement with the insulating layer so as to seal the inter-electrode surface area.
摘要翻译： 制造具有钝化表面的半导体器件的方法包括在衬底上提供接触层以便限定电极间表面积。 可以相对于彼此和基板和接触层选择性地蚀刻的第一层和绝缘层沉积在接触层和电极间表面区域上。 分别选择性地蚀刻绝缘层和第一层以限定电极接触面积并暴露电极间表面积。 暴露的电极间表面积在第一层蚀刻之前或期间被钝化。 在与绝缘层邻接的电极接触区域中形成金属接触，以密封电极间表面积。
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9.发明授权Method of manufacturing a gate structure for a metal semiconductor field effect transistor 失效制造金属半导体场效应晶体管的栅极结构的方法
公开(公告)号：US5688703A
公开(公告)日：1997-11-18
申请号：US523710
申请日：1995-09-05
IPC分类号： H01L21/285 , H01L21/335 , H01L21/338 , H01L29/08 , H01L29/423
CPC分类号： H01L29/66878 , H01L21/28581 , H01L21/28587 , H01L29/0891 , H01L29/42316 , H01L29/66462 , Y10S148/105 , Y10S148/14
摘要： A method of manufacturing a gate structure (19) for a semiconductor device (10) utilizes a dielectric layer (17) containing aluminum to protect the surface of a substrate (11) from residues resulting from deposition and etching of the gate structure (19). The gate structure (19) forms a refractory contact to the substrate (11), and the source and drain regions (26) are self-aligned to the gate structure (19). Semiconductor devices manufactured using methods in accordance with the present invention are observed to have a higher breakdown voltage and a higher transconductance, among other improved electrical performance characteristics.
摘要翻译： 制造半导体器件（10）的栅极结构（19）的方法利用包含铝的电介质层（17）来保护基板（11）的表面免受由栅极结构（19）的沉积和蚀刻所导致的残留物的影响， 。 栅极结构（19）与衬底（11）形成难熔接触，并且源极和漏极区域（26）与栅极结构（19）自对准。 观察到使用根据本发明的方法制造的半导体器件具有更高的击穿电压和更高的跨导以及其它改进的电气性能特性。
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公开(公告)号：US5733827A
公开(公告)日：1998-03-31
申请号：US557405
申请日：1995-11-13
IPC分类号： H01L21/285 , H01L21/338 , H01L23/485 , H01L21/28 , H01L21/337
CPC分类号： H01L29/66863 , H01L21/28587 , H01L23/485 , H01L2924/0002
摘要： A method of fabricating semiconductor devices with a passivated surface includes providing first cap and etch stop layers and second cap and etch stop layers with a contact layer thereon so as to define an inter-electrode surface area. A first layer and an insulating layer, which are selectively etchable relative to each other, are deposited on the contact layer and the inter-electrode surface area. The insulating layer and the first layer are individually etched to define an electrode contact area and to expose the inter-electrode surface area. Portions of the first etch stop and cap layers remaining in the contact area are selectively removed and a metal contact is formed in the contact area in abutting engagement with the insulating layer so as to seal the inter-electrode surface area.
摘要翻译： 制造具有钝化表面的半导体器件的方法包括提供第一帽和蚀刻停止层以及其上具有接触层的第二帽和蚀刻停止层，以限定电极间表面积。 相对于彼此可选择性地蚀刻的第一层和绝缘层沉积在接触层和电极间表面区域上。 绝缘层和第一层被单独蚀刻以限定电极接触面积并暴露电极间表面积。 选择性地除去残留在接触区域中的第一蚀刻停止层和盖层的部分，并且在与绝缘层邻接接合的接触区域中形成金属接触，以密封电极间表面积。
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