公开(公告)号：US06764949B2

公开(公告)日：2004-07-20

申请号：US10334392

申请日：2002-12-30

申请人： Douglas J. Bonser ,  Marina V. Plat ,  Chih Yuh Yang ,  Scott A. Bell ,  Darin Chan ,  Philip A. Fisher ,  Christopher F. Lyons ,  Mark S. Chang ,  Pei-Yuan Gao ,  Marilyn I. Wright ,  Lu You ,  Srikanteswara Dakshina-Murthy

发明人： Douglas J. Bonser ,  Marina V. Plat ,  Chih Yuh Yang ,  Scott A. Bell ,  Darin Chan ,  Philip A. Fisher ,  Christopher F. Lyons ,  Mark S. Chang ,  Pei-Yuan Gao ,  Marilyn I. Wright ,  Lu You ,  Srikanteswara Dakshina-Murthy

IPC分类号： H01L2144

CPC分类号： H01L21/32139 ,  H01L21/0332

摘要： A hardmask stack is comprised of alternating layers of doped amorphous carbon and undoped amorphous carbon. The undoped amorphous carbon layers serve as buffer layers that constrain the effects of compressive stress within the doped amorphous carbon layers to prevent delamination. The stack is provided with a top capping layer. The layer beneath the capping layer is preferably undoped amorphous carbon to reduce photoresist poisoning. An alternative hardmask stack is comprised of alternating layers of capping material and amorphous carbon. The amorphous carbon layers may be doped or undoped. The capping material layers serve as buffer layers that constrain the effects of compressive stress within the amorphous carbon layers to prevent delamination. The top layer of the stack is formed of a capping material. The layer beneath the top layer is preferably undoped amorphous carbon to reduce photoresist poisoning. The lowest layer of the hardmask stack is preferably amorphous carbon to facilitate easy removal of the hardmask stack from underlying materials by an ashing process.

公开(公告)号：US06797552B1

公开(公告)日：2004-09-28

申请号：US10299434

申请日：2002-11-19

申请人： Mark S. Chang ,  Douglas J. Bonser ,  Marina V. Plat ,  Chih Yuh Yang ,  Scott A. Bell ,  Srikanteswara Dakshina-Murthy

发明人： Mark S. Chang ,  Douglas J. Bonser ,  Marina V. Plat ,  Chih Yuh Yang ,  Scott A. Bell ,  Srikanteswara Dakshina-Murthy

IPC分类号： H01L21336

CPC分类号： H01L21/823456 ,  H01L21/0332 ,  H01L21/31138 ,  H01L21/32137 ,  H01L21/32139

摘要： A layer of material is patterned anisotropically using a bi-layer hardmask structure. Residual photoresist from a photoresist mask used to pattern an upper layer of the bi-layer hardmask is removed prior to patterning of the polysilicon layer. Passivation agents are later introduced from an external source during patterning of the layer of material. This provides a substantially uniform supply of passivation agents to all parts of the layer of material as it is being etched, rather than relying on the generation of passivation agents from consumption of photoresist during etching, which can produce local non-uniformities of passivation agent availability owing to differences in photoresist thickness remaining on different sized features.

摘要翻译： 使用双层硬掩模结构各向异性地图案化材料层。 在用于图案化双层硬掩模的上层的光致抗蚀剂掩模的残余光致抗蚀剂在图案化多晶硅层之前被去除。 在图案化材料层之后，钝化剂随后从外部源引入。 这提供了当被蚀刻时材料层的所有部分基本上均匀地供应钝化剂，而不是依赖于在蚀刻期间消除光致抗蚀剂的钝化剂的产生，这可以产生钝化剂可用性的局部不均匀性 由于在不同尺寸的特征上残留的光刻胶厚度的差异。

公开(公告)号：US07268066B2

公开(公告)日：2007-09-11

申请号：US10922093

申请日：2004-08-19

申请人： Douglas J. Bonser ,  Marina V. Plat ,  Chih Yuh Yang ,  Scott A. Bell ,  Srikanteswara Dakshina-Murthy ,  Philip A. Fisher ,  Christopher F. Lyons

发明人： Douglas J. Bonser ,  Marina V. Plat ,  Chih Yuh Yang ,  Scott A. Bell ,  Srikanteswara Dakshina-Murthy ,  Philip A. Fisher ,  Christopher F. Lyons

IPC分类号： H01L21/4763

CPC分类号： H01L29/66477 ,  H01L21/28123 ,  H01L29/1045 ,  H01L29/1054 ,  H01L29/665

摘要： To reduce the width of a MOSFET gate, the gate is formed with a hardmask formed thereupon. An isotropic etch is then performed to trim the gate in order to reduce the width of the gate. The resulting gate may be formed with a width that is narrower than a minimum width achievable solely through conventional projection lithography techniques.

摘要翻译： 为了减小MOSFET栅极的宽度，栅极形成有在其上形成的硬掩模。 然后执行各向同性蚀刻以修剪栅极，以便减小栅极的宽度。 所形成的栅极可以形成为比仅通过常规投影光刻技术可实现的最小宽度窄的宽度。

公开(公告)号：US06849530B2

公开(公告)日：2005-02-01

申请号：US10334337

申请日：2002-12-30

申请人： Douglas J. Bonser ,  Marina V. Plat ,  Chih Yuh Yang ,  Scott A. Bell ,  Srikanteswara Dakshina-Murthy ,  Philip A. Fisher ,  Christopher F. Lyons

发明人： Douglas J. Bonser ,  Marina V. Plat ,  Chih Yuh Yang ,  Scott A. Bell ,  Srikanteswara Dakshina-Murthy ,  Philip A. Fisher ,  Christopher F. Lyons

IPC分类号： H01L21/28 ,  H01L21/4763

CPC分类号： H01L21/28123

摘要： To reduce the width of a MOSFET gate, the gate is formed with a hardmask formed thereupon. An isotropic etch is then performed to trim the gate in order to reduce the width of the gate. The resulting gate may be formed with a width that is narrower than a minimum width achievable solely through conventional projection lithography techniques.

公开(公告)号：US06773998B1

公开(公告)日：2004-08-10

申请号：US10445129

申请日：2003-05-20

申请人： Philip A. Fisher ,  Marina V. Plat ,  Chih-Yuh Yang ,  Christopher F. Lyons ,  Scott A. Bell ,  Douglas J. Bonser ,  Lu You ,  Srikanteswara Dakshina-Murthy

发明人： Philip A. Fisher ,  Marina V. Plat ,  Chih-Yuh Yang ,  Christopher F. Lyons ,  Scott A. Bell ,  Douglas J. Bonser ,  Lu You ,  Srikanteswara Dakshina-Murthy

IPC分类号： H01L21336

CPC分类号： H01L21/0276 ,  H01L21/0332 ,  H01L21/28123 ,  H01L21/31116 ,  H01L21/3146 ,  H01L21/32137 ,  H01L21/32139

摘要： A method for an integrated circuit includes the use of an amorphous carbon ARC mask. A layer of amorphous carbon material is deposited above a layer of conductive material, and a layer of anti-reflective coating (ARC) material is deposited over the layer of amorphous carbon material. The layer of amorphous carbon material and the layer of ARC material are etched to form a mask comprising an ARC material portion and an amorphous carbon portion. A feature may then be formed in the layer of conductive material by etching the layer of conductive material in accordance with the mask.

摘要翻译： 集成电路的方法包括使用无定形碳ARC掩模。 一层非晶碳材料沉积在导电材料层上方，并且一层抗反射涂层（ARC）材料沉积在无定形碳材料层上。 蚀刻无定形碳材料层和ARC材料层以形成包含ARC材料部分和无定形碳部分的掩模。 然后可以通过根据掩模蚀刻导电材料层而在导电材料层中形成特征。

公开(公告)号：US06750127B1

公开(公告)日：2004-06-15

申请号：US10367407

申请日：2003-02-14

申请人： Mark S. Chang ,  Darin Chan ,  Chih Yuh Yang ,  Lu You ,  Scott A. Bell ,  Srikanteswara Dakshina-Murthy ,  Douglas J. Bonser

发明人： Mark S. Chang ,  Darin Chan ,  Chih Yuh Yang ,  Lu You ,  Scott A. Bell ,  Srikanteswara Dakshina-Murthy ,  Douglas J. Bonser

IPC分类号： H01L213205

CPC分类号： H01L21/32139 ,  H01L21/0332 ,  H01L21/0337

摘要： An amorphous carbon layer is implanted with one or more dopants that enhance the etch resistivity of the amorphous carbon to etchants such as chlorine and HBr that are typically used to etch polysilicon. Such a layer may be pattern to form a handmask for etching polysilicon that provides improved pattern transfer accuracy compared to conventional undoped amorphous carbon.

摘要翻译： 注入一个或多个掺杂剂的无定形碳层，其增强无定形碳对通常用于蚀刻多晶硅的蚀刻剂如氯和HBr的蚀刻电阻率。 这样的层可以被图案化以形成用于蚀刻多晶硅的手掩模，其与常规未掺杂的无定形碳相比提供改进的图案转印精度。

公开(公告)号：US07122455B1

公开(公告)日：2006-10-17

申请号：US10790567

申请日：2004-03-01

申请人： Christopher F. Lyons ,  Marina V. Plat ,  Srikanteswara Dakshina-Murthy ,  Scott A. Bell ,  Cyrus E. Tabery

发明人： Christopher F. Lyons ,  Marina V. Plat ,  Srikanteswara Dakshina-Murthy ,  Scott A. Bell ,  Cyrus E. Tabery

IPC分类号： H01L21/3205

CPC分类号： H01L21/32139 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/28035 ,  H01L21/28123 ,  Y10S438/942 ,  Y10S438/947

摘要： For patterning an IC (integrated circuit) material, a rigid organic under-layer is formed over the IC material, and the rigid organic under-layer is patterned to form a rigid organic mask structure. In addition, the rigid organic mask structure is trimmed to lower a critical dimension of the rigid organic mask structure beyond the limitations of traditional BARC mask structures. Any portion of the IC material not under the rigid organic mask structure is etched away to form an IC structure.

摘要翻译： 为了图案化IC（集成电路）材料，在IC材料之上形成刚性有机底层，并且将刚性有机底层图案化以形成刚性有机掩模结构。 此外，修剪刚性有机掩模结构以降低刚性有机掩模结构的临界尺寸超出传统BARC掩模结构的限制。 不会在刚性有机掩模结构下面的IC材料的任何部分被蚀刻掉以形成IC结构。

公开(公告)号：US07052921B1

公开(公告)日：2006-05-30

申请号：US10934192

申请日：2004-09-03

申请人： Marina V. Plat ,  Bhanwar Singh ,  Calvin T. Gabriel ,  Christopher F. Lyons ,  Scott A. Bell ,  Ramkumar Subramanian ,  Srikanteswara Dakshina-Murthy

发明人： Marina V. Plat ,  Bhanwar Singh ,  Calvin T. Gabriel ,  Christopher F. Lyons ,  Scott A. Bell ,  Ramkumar Subramanian ,  Srikanteswara Dakshina-Murthy

IPC分类号： H01L21/66

CPC分类号： G03F7/70625 ,  G03F7/70608 ,  H01L22/12

摘要： The present invention uses in situ scatterometry to determine if a defect (e.g., photoresist erosion, photoresist bending and pattern collapse) is present on a wafer. In one embodiment, in situ scatterometry is used to detect a pattern integrity defect associated with the layer of photoresist. In situ scatterometry produces diffraction data associated with the thickness of the photoresist patterned mask. This data is compared to a model of diffraction data associated with a suitable photoresist thickness. If the measured diffraction data is within an acceptable range, the next step of the photolithography process is carried out. However, if the measured thickness is outside of the suitable range, a defect is detected, and the wafer may be sent for re-working or re-patterned prior to main etch, thereby preventing unnecessary wafer scrap. Another aspect of the present invention allows for a feedback control mechanism to alter a physical parameter of the photolithographic process based upon the in situ scatterometry measurements.

摘要翻译： 本发明使用原位散射法来确定晶片上是否存在缺陷（例如，光致抗蚀剂侵蚀，光致抗蚀剂弯曲和图案崩溃）。 在一个实施例中，原位散射法用于检测与光致抗蚀剂层相关联的图案完整性缺陷。 原位散射法产生与光致抗蚀剂图案掩模的厚度相关的衍射数据。 将该数据与与合适的光致抗蚀剂厚度相关联的衍射数据的模型进行比较。 如果测量的衍射数据在可接受的范围内，则进行光刻工艺的下一步骤。 然而，如果测量的厚度在合适的范围之外，则检测到缺陷，并且可以在主蚀刻之前将晶片发送用于再加工或重新图案化，从而防止不必要的晶片废料。 本发明的另一方面允许反馈控制机制基于原位散射测量来改变光刻工艺的物理参数。

公开(公告)号：US06900139B1

公开(公告)日：2005-05-31

申请号：US10135175

申请日：2002-04-30

申请人： Srikanteswara Dakshina-Murthy ,  Douglas J. Bonser ,  Karen Turnquest

发明人： Srikanteswara Dakshina-Murthy ,  Douglas J. Bonser ,  Karen Turnquest

IPC分类号： H01L21/311 ,  H01L21/3213 ,  H01L21/4763 ,  H01L21/768

CPC分类号： H01L21/31138 ,  H01L21/32139 ,  H01L21/76838

摘要： A method for forming semiconductor features, e.g., gates, line widths, thicknesses and spaces, produced by a photoresist trim procedure, in a closed loop process is presented. The methodology enables the use of optical emission spectroscopy and/or optical interferometry techniques for endpoint monitoring during resist trim etching of photoresist structures. Various types of material layers underlying photoresist structures are employed in order to provide an endpoint signal to enable closed loop control, with resultant improved targeting of photoresist mask and reproducibility. In addition, the method provides for in situ etch rate monitoring, and is not adversely affected by etch rate variances within an etching chamber during an etch process.

摘要翻译： 提出了一种用于在闭环过程中形成由光致抗蚀剂修整过程产生的半导体特征（例如栅极，线宽，厚度和空间）的方法。 该方法使得能够在抗蚀剂修饰蚀刻光致抗蚀剂结构期间使用光发射光谱学和/或光学干涉测量技术来进行端点监测。 采用各种类型的光致抗蚀剂结构下面的材料层，以提供端点信号以实现闭环控制，从而改善光致抗蚀剂掩模的靶向性和再现性。 此外，该方法提供了原位蚀刻速率监测，并且不会在蚀刻工艺期间蚀刻室内的蚀刻速率变化受到不利影响。

公开(公告)号：US06673635B1

公开(公告)日：2004-01-06

申请号：US10185780

申请日：2002-06-28

申请人： Kay Hellig ,  Douglas J. Bonser ,  Srikanteswara Dakshina-Murthy

发明人： Kay Hellig ,  Douglas J. Bonser ,  Srikanteswara Dakshina-Murthy

IPC分类号： H01L2100

CPC分类号： H01L23/544 ,  H01L21/30604 ,  H01L21/3083 ,  H01L21/31116 ,  H01L21/31144 ,  H01L2223/54426 ,  H01L2223/54453 ,  H01L2924/0002 ,  H01L2924/00

摘要： Methods are presented for fabrication of alignment features of a desired depth, and shallow trench isolation (STI) features in Silicon-On-Insulator (SOI) material. Specific embodiments require no more than two lithography and etch processes, which represents an improvement over current methodology requiring three lithography and etch processes in order to produce the desired features during manufacture of a semiconductor device.

摘要翻译： 提出了用于制造所需深度的对准特征以及绝缘体上硅（SOI）材料中的浅沟槽隔离（STI）特征的方法。 具体实施方案要求不超过两个光刻和蚀刻工艺，其代表了需要三次光刻和蚀刻工艺的电流方法的改进，以便在制造半导体器件期间产生期望的特征。