公开(公告)号：US06797552B1

公开(公告)日：2004-09-28

申请号：US10299434

申请日：2002-11-19

申请人： Mark S. Chang ,  Douglas J. Bonser ,  Marina V. Plat ,  Chih Yuh Yang ,  Scott A. Bell ,  Srikanteswara Dakshina-Murthy

发明人： Mark S. Chang ,  Douglas J. Bonser ,  Marina V. Plat ,  Chih Yuh Yang ,  Scott A. Bell ,  Srikanteswara Dakshina-Murthy

IPC分类号： H01L21336

CPC分类号： H01L21/823456 ,  H01L21/0332 ,  H01L21/31138 ,  H01L21/32137 ,  H01L21/32139

摘要： A layer of material is patterned anisotropically using a bi-layer hardmask structure. Residual photoresist from a photoresist mask used to pattern an upper layer of the bi-layer hardmask is removed prior to patterning of the polysilicon layer. Passivation agents are later introduced from an external source during patterning of the layer of material. This provides a substantially uniform supply of passivation agents to all parts of the layer of material as it is being etched, rather than relying on the generation of passivation agents from consumption of photoresist during etching, which can produce local non-uniformities of passivation agent availability owing to differences in photoresist thickness remaining on different sized features.

摘要翻译： 使用双层硬掩模结构各向异性地图案化材料层。 在用于图案化双层硬掩模的上层的光致抗蚀剂掩模的残余光致抗蚀剂在图案化多晶硅层之前被去除。 在图案化材料层之后，钝化剂随后从外部源引入。 这提供了当被蚀刻时材料层的所有部分基本上均匀地供应钝化剂，而不是依赖于在蚀刻期间消除光致抗蚀剂的钝化剂的产生，这可以产生钝化剂可用性的局部不均匀性 由于在不同尺寸的特征上残留的光刻胶厚度的差异。

公开(公告)号：US06764949B2

公开(公告)日：2004-07-20

申请号：US10334392

申请日：2002-12-30

申请人： Douglas J. Bonser ,  Marina V. Plat ,  Chih Yuh Yang ,  Scott A. Bell ,  Darin Chan ,  Philip A. Fisher ,  Christopher F. Lyons ,  Mark S. Chang ,  Pei-Yuan Gao ,  Marilyn I. Wright ,  Lu You ,  Srikanteswara Dakshina-Murthy

发明人： Douglas J. Bonser ,  Marina V. Plat ,  Chih Yuh Yang ,  Scott A. Bell ,  Darin Chan ,  Philip A. Fisher ,  Christopher F. Lyons ,  Mark S. Chang ,  Pei-Yuan Gao ,  Marilyn I. Wright ,  Lu You ,  Srikanteswara Dakshina-Murthy

IPC分类号： H01L2144

CPC分类号： H01L21/32139 ,  H01L21/0332

摘要： A hardmask stack is comprised of alternating layers of doped amorphous carbon and undoped amorphous carbon. The undoped amorphous carbon layers serve as buffer layers that constrain the effects of compressive stress within the doped amorphous carbon layers to prevent delamination. The stack is provided with a top capping layer. The layer beneath the capping layer is preferably undoped amorphous carbon to reduce photoresist poisoning. An alternative hardmask stack is comprised of alternating layers of capping material and amorphous carbon. The amorphous carbon layers may be doped or undoped. The capping material layers serve as buffer layers that constrain the effects of compressive stress within the amorphous carbon layers to prevent delamination. The top layer of the stack is formed of a capping material. The layer beneath the top layer is preferably undoped amorphous carbon to reduce photoresist poisoning. The lowest layer of the hardmask stack is preferably amorphous carbon to facilitate easy removal of the hardmask stack from underlying materials by an ashing process.

公开(公告)号：US06750127B1

公开(公告)日：2004-06-15

申请号：US10367407

申请日：2003-02-14

申请人： Mark S. Chang ,  Darin Chan ,  Chih Yuh Yang ,  Lu You ,  Scott A. Bell ,  Srikanteswara Dakshina-Murthy ,  Douglas J. Bonser

发明人： Mark S. Chang ,  Darin Chan ,  Chih Yuh Yang ,  Lu You ,  Scott A. Bell ,  Srikanteswara Dakshina-Murthy ,  Douglas J. Bonser

IPC分类号： H01L213205

CPC分类号： H01L21/32139 ,  H01L21/0332 ,  H01L21/0337

摘要： An amorphous carbon layer is implanted with one or more dopants that enhance the etch resistivity of the amorphous carbon to etchants such as chlorine and HBr that are typically used to etch polysilicon. Such a layer may be pattern to form a handmask for etching polysilicon that provides improved pattern transfer accuracy compared to conventional undoped amorphous carbon.

摘要翻译： 注入一个或多个掺杂剂的无定形碳层，其增强无定形碳对通常用于蚀刻多晶硅的蚀刻剂如氯和HBr的蚀刻电阻率。 这样的层可以被图案化以形成用于蚀刻多晶硅的手掩模，其与常规未掺杂的无定形碳相比提供改进的图案转印精度。

公开(公告)号：US06864556B1

公开(公告)日：2005-03-08

申请号：US10335445

申请日：2002-12-31

申请人： Lu You ,  Marina V. Plat ,  Chih Yuh Yang ,  Scott A. Bell ,  Richard J. Huang ,  Christopher F. Lyons ,  Mark S. Chang ,  Marilyn I. Wright

发明人： Lu You ,  Marina V. Plat ,  Chih Yuh Yang ,  Scott A. Bell ,  Richard J. Huang ,  Christopher F. Lyons ,  Mark S. Chang ,  Marilyn I. Wright

IPC分类号： G03F7/09 ,  H01L21/033 ,  H01L21/28 ,  H01L21/3213 ,  H01L21/47 ,  H01L31/0232

CPC分类号： H01L21/32139 ,  G03F7/091 ,  H01L21/0332 ,  H01L21/28123 ,  H01L29/785

摘要： A bottom anti-reflective coating comprising an organic polymer layer having substantially no nitrogen and a low compressive stress in relation to a polysilicon layer is employed as the lower layer of a bi-layer antireflective coating/hardmask structure to reduce deformation of a pattern to be formed in a patternable layer. The organic polymer layer is substantially transparent to visible radiation, enabling better detection of alignment marks during a semiconductor device fabrication process and improving overlay accuracy. The organic polymer layer provides excellent step coverage and may be advantageously used in the fabrication of structures such as FinFETs.

摘要翻译： 采用底层抗反射涂层，其包含基本上不含氮的有机聚合物层和相对于多晶硅层的低压缩应力作为双层抗反射涂层/硬掩模结构的下层，以减少图案的变形 形成在可图案层中。 有机聚合物层对可见辐射基本上是透明的，能够在半导体器件制造过程中更好地检测对准标记并提高覆盖精度。 有机聚合物层提供优异的台阶覆盖，并且可以有利地用于制造诸如FinFET的结构。

公开(公告)号：US06812077B1

公开(公告)日：2004-11-02

申请号：US10299433

申请日：2002-11-19

申请人： Darin Chan ,  Douglas J. Bonser ,  Mark S. Chang

发明人： Darin Chan ,  Douglas J. Bonser ,  Mark S. Chang

IPC分类号： H01L2100

CPC分类号： H01L21/32105 ,  H01L21/28088 ,  H01L21/28123

摘要： Patterning of a gate line is terminated prior to etching completely through the conductive layer from which it is patterned. Surfaces of the conductive layer are then reacted in a reactive atmosphere, and the reacted surfaces are removed, creating a narrow gate line. The protection provided by the remaining portion of the conductive layer during reaction protects the lower corners of the patterned feature from undercutting growth of reacted material. Alternatively, a gate line is patterned from a multi-layered conductive structure that includes a lower conductive layer and an upper conductive layer that exhibits higher reactivity in a reactive atmosphere than the lower layer. The upper layer is patterned and then the structure is reacted in the reactive atmosphere. Reacted portions of the upper layer are then removed and the lower layer is patterned in a self-aligned manner to complete the formation of a gate line and gate insulator.

摘要翻译： 在蚀刻完全通过图案化的导电层之前终止栅极线的图案化。 然后在反应性气氛中使导电层的表面反应，除去反应的表面，产生窄的栅极线。 在反应期间由导电层的剩余部分提供的保护保护图案化特征的下角部不被反应材料的底切生长。 或者，栅极线从包括下导电层和上导电层的多层导电结构图案化，反应性气氛中的反应性比下层高。 上层被图案化，然后结构在反应性气氛中反应。 然后去除上层的反应部分，并且以自对准方式图案化下层，以完成栅极线和栅极绝缘体的形成。

公开(公告)号：US06200884B1

公开(公告)日：2001-03-13

申请号：US09364976

申请日：1999-07-31

申请人： Chih-Yuh Yang ,  Mark S. Chang

发明人： Chih-Yuh Yang ,  Mark S. Chang

IPC分类号： H01L21425

CPC分类号： H01L21/0274 ,  H01L21/266 ,  H01L21/31138

摘要： A method for making a ULSI MOSFET chip includes masking areas such as transistor gates with photoresist mask regions. Prior to ion implantation, the top shoulders of the mask regions are etched away, to round off the shoulders. This promotes subsequent efficient quasi-vertical ion implantation, commonly referred to as “high aspect ratio implantation” in the semiconductor industry.

摘要翻译： 制造ULSI MOSFET芯片的方法包括具有光致抗蚀剂掩模区域的诸如晶体管栅极的掩模区域。 在离子注入之前，掩模区域的顶部肩部被蚀刻掉，从而使肩部圆整。 这促进随后的有效的准垂直离子注入，在半导体工业中通常被称为“高纵横比植入”。

公开(公告)号：US20080142873A1

公开(公告)日：2008-06-19

申请号：US11611856

申请日：2006-12-16

申请人： Angela T. Hui ,  Mark S. Chang ,  Kuo-Tung Chang ,  Scott A. Bell

发明人： Angela T. Hui ,  Mark S. Chang ,  Kuo-Tung Chang ,  Scott A. Bell

IPC分类号： H01L29/792 ,  H01L21/28

CPC分类号： H01L27/115 ,  H01L27/11568

摘要： A method for forming an integrated circuit system is provided including forming a semi-conducting layer over a substrate, forming a spacer stack having a gap filler adjacent to the semi-conducting layer and a inter-layer dielectric over the gap filler, forming a transition layer having a recess over the semi-conducting layer and adjacent to the spacer stack, and forming a metal layer in the recess.

摘要翻译： 提供了一种用于形成集成电路系统的方法，包括在衬底上形成半导电层，形成间隔层叠层，其间隔填充物与半导体层相邻，间隙填料上形成层间电介质，形成过渡层 该层在半导体层上具有凹陷并且与间隔物堆叠相邻，并且在凹部中形成金属层。

公开(公告)号：US07361588B2

公开(公告)日：2008-04-22

申请号：US11098049

申请日：2005-04-04

申请人： Phillip L. Jones ,  Mark S. Chang ,  Scott A. Bell

发明人： Phillip L. Jones ,  Mark S. Chang ,  Scott A. Bell

IPC分类号： H01L21/4763

CPC分类号： H01L21/32139 ,  H01L21/3088 ,  H01L21/31144

摘要： A method of reducing critical dimensions of a feature in a anti-reflective coating layer structure can utilize a polymerizing agent. The anti-reflective coating structure can be utilized to form various integrated circuit structures. The anti-reflective coating can be utilized to form gate stacks comprised of polysilicon and a dielectric layer, conductive lines, or other IC structure. The polymerizing agent can include carbon, hydrogen and fluorine.

摘要翻译： 降低抗反射涂层结构中的特征的关键尺寸的方法可以利用聚合剂。 抗反射涂层结构可用于形成各种集成电路结构。 抗反射涂层可用于形成由多晶硅和电介质层，导电线或其它IC结构组成的栅叠层。 聚合剂可以包括碳，氢和氟。

公开(公告)号：US08283718B2

公开(公告)日：2012-10-09

申请号：US11611856

申请日：2006-12-16

申请人： Angela T. Hui ,  Mark S. Chang ,  Kuo-Tung Chang ,  Scott A. Bell

发明人： Angela T. Hui ,  Mark S. Chang ,  Kuo-Tung Chang ,  Scott A. Bell

IPC分类号： H01L29/792

CPC分类号： H01L27/115 ,  H01L27/11568

摘要： A method for forming an integrated circuit system is provided including forming a semi-conducting layer over a substrate, forming a spacer stack having a gap filler adjacent to the semi-conducting layer and a inter-layer dielectric over the gap filler, forming a transition layer having a recess over the semi-conducting layer and adjacent to the spacer stack, and forming a metal layer in the recess.

摘要翻译： 提供了一种用于形成集成电路系统的方法，包括在衬底上形成半导电层，形成间隔层叠层，其间隔填充物与半导体层相邻，间隙填料上形成层间电介质，形成过渡层 该层在半导体层上具有凹陷并且与间隔物堆叠相邻，并且在凹部中形成金属层。

公开(公告)号：US08329530B1

公开(公告)日：2012-12-11

申请号：US13566741

申请日：2012-08-03

申请人： Mark S. Chang ,  Hao Fang ,  King Wai Kelwin Ko

发明人： Mark S. Chang ,  Hao Fang ,  King Wai Kelwin Ko

IPC分类号： H01L31/0328 ,  H01L31/0336 ,  H01L31/072 ,  H01L31/109

CPC分类号： H01L27/11521 ,  H01L21/76816 ,  H01L27/115

摘要： A method and system for providing at least one contact in a flash memory device is disclosed. The flash memory device includes a plurality of gate stacks and at lease one component including a polysilicon layer as a top surface. The method and system further include forming a silicide on the top surface of the polysilicon layer and providing an insulating layer covering the plurality of gate stacks, the at least one component and the silicide. The method and system also include etching the insulating layer to provide at least one contact hole. The insulating layer etching step uses the silicide as an etch stop layer to ensure that the insulating etching step does not etch through the polysilicon layer. The method and system also include filling the at least one contact hole with a conductor.

摘要翻译： 公开了一种用于在闪速存储器件中提供至少一个触点的方法和系统。 闪速存储器件包括多个栅极堆叠，并且至少包括一个包括多晶硅层作为顶表面的部件。 该方法和系统还包括在多晶硅层的顶表面上形成硅化物，并提供覆盖多个栅叠层，至少一个元件和硅化物的绝缘层。 该方法和系统还包括蚀刻绝缘层以提供至少一个接触孔。 绝缘层蚀刻步骤使用硅化物作为蚀刻停止层，以确保绝缘蚀刻步骤​​不会蚀刻通过多晶硅层。 该方法和系统还包括用导体填充至少一个接触孔。