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16 条记录 (耗时 0.021 秒)

    Method of manufacturing spacer etch mask for silicon-oxide-nitride-oxide-silicon (SONOS) type nonvolatile memory
    2.
    发明授权
    Method of manufacturing spacer etch mask for silicon-oxide-nitride-oxide-silicon (SONOS) type nonvolatile memory 有权
    制造用于氧化硅 - 氧化物 - 氧化物 - 硅（SONOS）型非易失性存储器的间隔物蚀刻掩模的方法

    公开(公告)号：US06465303B1

    公开(公告)日：2002-10-15

    申请号：US09885490

    申请日：2001-06-20

    申请人： Mark T. Ramsbey ,  Narbeh Derhacobian ,  Janet Wang ,  Angela Hui ,  Tuan Pham ,  Ravi Sunkavalli ,  Mark Randolph

    发明人： Mark T. Ramsbey ,  Narbeh Derhacobian ,  Janet Wang ,  Angela Hui ,  Tuan Pham ,  Ravi Sunkavalli ,  Mark Randolph

    IPC分类号： H01L21336

    CPC分类号： H01L27/11568 ,  H01L27/105 ,  H01L27/11573

    摘要： One aspect of the present invention relates to a method of forming spacers in a silicon-oxide-nitride-oxide-silicon (SONOS) type nonvolatile semiconductor memory device, involving the steps of providing a semiconductor substrate having a core region and periphery region, the core region containing SONOS type memory cells and the periphery region containing gate transistors; implanting a first implant into the core region and a first implant into the periphery region of the semiconductor substrate; forming a spacer material over the semiconductor substrate; masking the core region and forming spacers adjacent the gate transistors in the periphery region; and implanting a second implant into the periphery region of the semiconductor substrate.

    摘要翻译： 本发明的一个方面涉及一种在氧化硅 - 氧化物 - 氧化物 - 硅（SONOS）型非易失性半导体存储器件中形成间隔物的方法，包括以下步骤：提供具有核心区域和外围区域的半导体衬底， 包含SONOS型存储单元的核心区域和包含栅极晶体管的外围区域; 将第一注入植入到所述芯区域中，并将第一注入植入所述半导体衬底的周边区域; 在所述半导体衬底上形成隔离材料; 掩蔽所述芯区域并在所述周边区域中形成与所述栅极晶体管相邻的间隔物; 以及将第二植入物植入所述半导体衬底的周边区域。

    Method of simultaneous formation of bitline isolation and periphery oxide
    3.
    发明授权
    Method of simultaneous formation of bitline isolation and periphery oxide 有权
    同时形成位线隔离和周边氧化物的方法

    公开(公告)号：US06468865B1

    公开(公告)日：2002-10-22

    申请号：US09723653

    申请日：2000-11-28

    申请人： Jean Y. Yang ,  Mark T. Ramsbey ,  Hidehiko Shiraiwa ,  Michael A. Van Buskirk ,  David M. Rogers ,  Ravi Sunkavalli ,  Janet Wang ,  Narbeh Derhacobian ,  Yider Wu

    发明人： Jean Y. Yang ,  Mark T. Ramsbey ,  Hidehiko Shiraiwa ,  Michael A. Van Buskirk ,  David M. Rogers ,  Ravi Sunkavalli ,  Janet Wang ,  Narbeh Derhacobian ,  Yider Wu

    IPC分类号： H01L21336

    CPC分类号： H01L27/11568 ,  H01L27/115

    摘要： One aspect of the present invention relates to a method of forming a non-volatile semiconductor memory device, involving the sequential or non-sequential steps of forming a charge trapping dielectric over a substrate, the substrate having a core region and a periphery region; removing at least a portion of the charge trapping dielectric in the periphery region; forming a gate dielectric in the periphery region; forming buried bitlines in the core region; removing at least a portion of the charge trapping dielectric positioned over the buried bitlines in the core region; forming a bitline isolation over the buried bitlines in the core region; and forming gates in the core region and the periphery region. Another aspect of the present invention relates to increasing the thickness of the gate dielectric in at least a portion of the periphery region simultaneously while forming the bitline isolation.

    摘要翻译： 本发明的一个方面涉及一种形成非挥发性半导体存储器件的方法，涉及在衬底上形成电荷俘获电介质的顺序或非顺序步骤，所述衬底具有芯区域和外围区域; 去除外围区域中的电荷捕获电介质的至少一部分; 在周边区域形成栅电介质; 在核心区域形成掩埋位线; 去除位于芯区域中的掩埋位线之上的电荷捕获电介质的至少一部分; 在核心区域的掩埋位线上形成位线隔离; 并且在芯区域和周边区域中形成栅极。 本发明的另一方面涉及在形成位线隔离的同时在周边区域的至少一部分中增加栅极电介质的厚度。

    Self-limiting multi-level programming states
    4.
    发明授权
    Self-limiting multi-level programming states 有权
    自限制多级编程状态

    公开(公告)号：US06233175B1

    公开(公告)日：2001-05-15

    申请号：US09693650

    申请日：2000-10-21

    申请人： Janet Wang ,  Ravi Sunkavalli

    发明人： Janet Wang ,  Ravi Sunkavalli

    IPC分类号： G11C1604

    CPC分类号： G11C16/12 ,  G11C11/5621 ,  G11C11/5628 ,  G11C11/5635

    摘要： A method of programming flash EEPROM devices that provides self-limiting multi-level programming states. Each cell in the flash EEPROM device can be programmed to have one of multiple threshold voltages. Each cell to be programmed has a programming voltage applied to the gate, a programming voltage applied to the drain and bias voltage applied to either the source (Vs) or to the substrate (Vsub) or both. The bias voltages Vs or Vsub are determined during a precharacterization procedure and each desired threshold voltage has a corresponding bias voltage Vs or Vsub that provides the desired threshold voltage during the programming procedure. The bias voltages Vs or Vsub are selected to provide self-limiting programming by the effective vertical field Ev=Vg −Vt−(either Vs or Vsub), where Vt increases during programming until the programming stops. The lateral field El=Vd−(either Vs and/or Vsub) is adjusted during programming to keep the lateral field El equal to Vd.

    摘要翻译： 编程提供自限制多级编程状态的闪存EEPROM器件的方法。 闪存EEPROM器件中的每个单元可以被编程为具有多个阈值电压之一。 要被编程的每个单元具有施加到栅极的编程电压，施加到漏极的编程电压和施加到源极（Vs）或衬底（Vsub）或两者的偏置电压。 偏置电压Vs或Vsub在预特性过程期间确定，并且每个期望的阈值电压具有在编程过程期间提供期望阈值电压的对应偏置电压Vs或Vsub。 选择偏置电压Vs或Vsub以通过有效垂直场Ev = Vg -Vt-（Vs或Vsub）提供自限制编程，其中Vt在编程期间增加直到编程停止。 在编程期间调整横向场El = Vd-（Vs和/或Vsub）以保持横向场El等于Vd。

    Non-uniform threshold voltage adjustment in flash eproms through gate work function alteration
    6.
    发明授权
    Non-uniform threshold voltage adjustment in flash eproms through gate work function alteration 失效
    通过门功功能改变，闪光eprom中的非均匀阈值电压调整

    公开(公告)号：US5888867A

    公开(公告)日：1999-03-30

    申请号：US23241

    申请日：1998-02-13

    申请人： Janet Wang ,  Scott D. Luning ,  Vei-Han Chan ,  Nicholas H. Tripsas

    发明人： Janet Wang ,  Scott D. Luning ,  Vei-Han Chan ,  Nicholas H. Tripsas

    IPC分类号： H01L21/28 ,  H01L21/3215 ,  H01L21/336 ,  H01L29/423 ,  H01L29/49 ,  H01L21/8247

    CPC分类号： H01L29/66825 ,  H01L21/2807 ,  H01L21/28105 ,  H01L21/32155 ,  H01L29/42324 ,  H01L29/4966

    摘要： Aspects for forming a Flash EPROM cell with an adjustable threshold voltage are described. In a method aspect, the method includes forming a substrate structure to establish a foundation for cell formation, and forming a gate structure with a floating gate layer comprising polysilicon-germanium (poly-SiGe) of a non-uniform Ge concentration on the substrate structure. The method further includes forming source and drain regions within the substrate structure, the drain region having a different threshold voltage than the source region. In a further aspect, a Flash EPROM cell with an adjustable threshold voltage includes a substrate structure as a foundation for the cell. The cell further includes a gate structure on the substrate structure, the gate structure comprising a floating gate layer of polysilicon-germanium (poly-SiGe) of non-uniform Ge concentration. Additionally, source and drain regions are included in the substrate structure bordering the gate structure, the drain region having a differing threshold voltage than the source region.

    摘要翻译： 描述了形成具有可调阈值电压的闪存EPROM单元的方面。 在方法方面，该方法包括形成衬底结构以建立细胞形成的基础，以及在衬底结构上形成具有包含不均匀Ge浓度的多晶锗（多晶硅）的浮栅的栅极结构 。 该方法还包括在衬底结构内形成源极和漏极区域，漏极区域具有与源极区域不同的阈值电压。 在另一方面，具有可调阈值电压的闪存EPROM单元包括作为单元的基础的衬底结构。 电池还包括在衬底结构上的栅极结构，栅极结构包括具有不均匀Ge浓度的多晶硅 - 锗（多晶SiGe）的浮栅。 此外，源极和漏极区域包括在与栅极结构接壤的衬底结构中，漏极区域具有与源极区域不同的阈值电压。

    Method of programming a non-volatile memory cell using a substrate bias
    8.
    发明授权
    Method of programming a non-volatile memory cell using a substrate bias 有权
    使用衬底偏置来编程非易失性存储单元的方法

    公开(公告)号：US06456536B1

    公开(公告)日：2002-09-24

    申请号：US09884409

    申请日：2001-06-19

    申请人： Daniel Sobek ,  Timothy J. Thurgate ,  Janet Wang ,  Narbeh Derhacobian

    发明人： Daniel Sobek ,  Timothy J. Thurgate ,  Janet Wang ,  Narbeh Derhacobian

    IPC分类号： G11C1604

    CPC分类号： G11C16/0475 ,  G11C11/5671 ,  G11C16/12

    摘要： A method of programming a memory cell with a substrate that includes a first region and a second region with a channel therebetween and a gate above the channel, and a charge trapping region that contains a first amount of charge. The method includes applying a constant first voltage across the gate, applying a second constant voltage across the first region and applying a third voltage that is constant and negative to the substrate so that the effect of spillover electrons is substantially reduced when compared with when the third constant voltage is absent.

    摘要翻译： 一种用衬底编程存储单元的方法，该衬底包括第一区域和具有通道的第二区域和沟道上方的栅极以及包含第一电荷量的电荷捕获区域。 该方法包括在栅极上施加恒定的第一电压，在第一区域上施加第二恒定电压，并向衬底施加恒定和负的第三电压，使得当与第三区域相比时，溢出电子的效应显着降低 不存在恒定电压。

    Read methods, circuits and systems for memory devices
    9.
    发明授权
    Read methods, circuits and systems for memory devices 有权
    读取存储器件的方法，电路和系统

    公开(公告)号：US08654561B1

    公开(公告)日：2014-02-18

    申请号：US13276763

    申请日：2011-10-19

    申请人： John Ross Jameson ,  John Dinh ,  Derric Lewis ,  Daniel Wang ,  Shane Charles Hollmer ,  Nad Edward Gilbert ,  Janet Wang

    发明人： John Ross Jameson ,  John Dinh ,  Derric Lewis ,  Daniel Wang ,  Shane Charles Hollmer ,  Nad Edward Gilbert ,  Janet Wang

    IPC分类号： G11C11/00

    CPC分类号： G11C11/1673 ,  G11C11/5685 ,  G11C13/0007 ,  G11C13/004 ,  G11C13/0061

    摘要： A memory device can include a plurality of programmable elements; at least one sense circuit that generates sense data values from detected impedances of accessed programmable elements; and at least one data store circuit that stores initial data values from the at least one sense circuit, and stores output data values from the at least one sense circuit after check conditions have been applied to at least one programmable element. The check conditions can induce a change in impedance for programmable elements programmed to at least one predetermined state. Methods can include reading data from at least one memory cell of a memory device comprising a plurality of such memory cells; if the read data has a first value, providing such data as an output value; and if the read data has a second value, repeating access to the memory cell to confirm the read data value.

    摘要翻译： 存储器件可以包括多个可编程元件; 至少一个感测电路，其从所访问的可编程元件的检测到的阻抗产生感测数据值; 以及至少一个数据存储电路，其存储来自所述至少一个感测电路的初始数据值，并且在检查条件已应用于至少一个可编程元件之后存储来自所述至少一个感测电路的输出数据值。 检查条件可以引起编程为至少一个预定状态的可编程元件的阻抗变化。 方法可以包括从包括多个这样的存储器单元的存储器件的至少一个存储器单元读取数据; 如果读取的数据具有第一值，则提供这样的数据作为输出值; 并且如果读取的数据具有第二值，则重复访问存储器单元以确认读取的数据值。