公开(公告)号：US07521376B2

公开(公告)日：2009-04-21

申请号：US11259165

申请日：2005-10-26

申请人： Martin M. Frank ,  Steven J. Koester ,  John A. Ott ,  Huiling Shang

发明人： Martin M. Frank ,  Steven J. Koester ,  John A. Ott ,  Huiling Shang

IPC分类号： H01L21/469

CPC分类号： H01L21/02052 ,  H01L21/02046 ,  H01L21/02175 ,  H01L21/0228 ,  H01L21/28255 ,  H01L21/306 ,  H01L21/31604 ,  H01L29/513 ,  H01L29/66181

摘要： A method and structure in which Ge-based semiconductor devices such as FETs and MOS capacitors can be obtained are provided. Specifically, the present invention provides a method of forming a semiconductor device including a stack including a dielectric layer and a conductive material located on and/or within a Ge-containing material (layer or wafer) in which the surface thereof is non-oxygen chalcogen rich. By providing a non-oxygen chalcogen rich interface, the formation of undesirable interfacial compounds during and after dielectric growth is suppressed and interfacial traps are reduced in density.

摘要翻译： 提供了可以获得诸如FET和MOS电容器的Ge基半导体器件的方法和结构。 具体地说，本发明提供了一种形成半导体器件的方法，该半导体器件包括一个包含电介质层和导电材料的叠层，该叠层位于其表面为非氧硫属元素的含Ge材料（层或晶片）之上和/或之内 丰富。 通过提供非氧贫硫族元素界面，抑制了电介质生长过程中和之后不希望的界面化合物的形成，并且界面陷阱的密度降低。

公开(公告)号：US20120190155A1

公开(公告)日：2012-07-26

申请号：US13440590

申请日：2012-04-05

申请人： Jack O. Chu ,  Guy M. Cohen ,  John A. Ott ,  Michael J. Rooks ,  Paul M. Solomon

发明人： Jack O. Chu ,  Guy M. Cohen ,  John A. Ott ,  Michael J. Rooks ,  Paul M. Solomon

IPC分类号： H01L21/336 ,  B82Y40/00

CPC分类号： H01L29/0665 ,  B82Y10/00 ,  H01L29/0673 ,  H01L29/458 ,  H01L29/7839 ,  H01L29/785 ,  H01L29/78618 ,  H01L29/78684 ,  H01L29/78696

摘要： A FET structure with a nanowire forming the FET channel, and doped source and drain regions formed by radial epitaxy from the nanowire body is disclosed. A top gated and a bottom gated nanowire FET structures are discussed. The source and drain fabrication can use either selective or non-selective epitaxy.

摘要翻译： 公开了具有形成FET沟道的纳米线的FET结构以及由纳米线体径向外延形成的掺杂源极和漏极区。 讨论了顶盖门控和底部门控纳米线FET结构。 源极和漏极制造可以使用选择性或非选择性外延。

公开(公告)号：US08138061B2

公开(公告)日：2012-03-20

申请号：US11031165

申请日：2005-01-07

申请人： Joel P. de Souza ,  John A. Ott ,  Alexander Reznicek ,  Devendra K. Sadana ,  Katherine L. Saenger

发明人： Joel P. de Souza ,  John A. Ott ,  Alexander Reznicek ,  Devendra K. Sadana ,  Katherine L. Saenger

IPC分类号： H01L21/46

CPC分类号： H01L21/187 ,  H01L21/76251

摘要： The present invention provides a method for removing or reducing the thickness of ultrathin interfacial oxides remaining at Si—Si interfaces after silicon wafer bonding. In particular, the invention provides a method for removing ultrathin interfacial oxides remaining after hydrophilic Si—Si wafer bonding to create bonded Si—Si interfaces having properties comparable to those achieved with hydrophobic bonding. Interfacial oxide layers of order of about 2 to about 3 nm are dissolved away by high temperature annealing, for example, an anneal at 1300°-1330° C. for 1-5 hours. The inventive method is used to best advantage when the Si surfaces at the bonded interface have different surface orientations, for example, when a Si surface having a (100) orientation is bonded to a Si surface having a (110) orientation. In a more general aspect of the invention, the similar annealing processes may be used to remove undesired material disposed at a bonded interface of two silicon-containing semiconductor materials. The two silicon-containing semiconductor materials may be the same or different in surface crystal orientation, microstructure (single-crystal, polycrystalline, or amorphous), and composition.

摘要翻译： 本发明提供一种在硅晶片接合之后去除或减少残留在Si-Si界面处的超薄界面氧化物的厚度的方法。 特别地，本发明提供了一种去除在亲水性Si-Si晶片接合之后残留的超薄界面氧化物以产生具有与用疏水性接合实现的特性相当的性质的结合Si-Si界面的方法。 约2至约3nm的界面氧化物层通过高温退火（例如1300°-1330℃退火1-5小时）被溶解掉。 当粘合界面处的Si表面具有不同的表面取向时，例如当具有（100）取向的Si表面被结合到具有（110）取向的Si表面时，本发明的方法被用于最好的优点。 在本发明的更一般的方面中，类似的退火工艺可用于去除设置在两个含硅半导体材料的键合界面处的不期望的材料。 两种含硅半导体材料在表面晶体取向，微结构（单晶，多晶或无定形）和组成上可以相同或不同。

公开(公告)号：US08053330B2

公开(公告)日：2011-11-08

申请号：US12538115

申请日：2009-08-08

申请人： Joel P. de Souza ,  John A. Ott ,  Alexander Reznicek ,  Devendra K. Sadana ,  Katherine L. Saenger

发明人： Joel P. de Souza ,  John A. Ott ,  Alexander Reznicek ,  Devendra K. Sadana ,  Katherine L. Saenger

IPC分类号： H01L21/46

CPC分类号： H01L21/187 ,  H01L21/76251

摘要： The present invention provides a method for removing or reducing the thickness of ultrathin interfacial oxides remaining at Si—Si interfaces after silicon wafer bonding. In particular, the invention provides a method for removing ultrathin interfacial oxides remaining after hydrophilic Si—Si wafer bonding to create bonded Si—Si interfaces having properties comparable to those achieved with hydrophobic bonding. Interfacial oxide layers of order of about 2 to about 3 nm are dissolved away by high temperature annealing, for example, an anneal at 1300°-1330° C. for 1-5 hours. The inventive method is used to best advantage when the Si surfaces at the bonded interface have different surface orientations, for example, when a Si surface having a (100) orientation is bonded to a Si surface having a (110) orientation. In a more general aspect of the invention, the similar annealing processes may be used to remove undesired material disposed at a bonded interface of two silicon-containing semiconductor materials. The two silicon-containing semiconductor materials may be the same or different in surface crystal orientation, microstructure (single-crystal, polycrystalline, or amorphous), and composition.

摘要翻译： 本发明提供一种在硅晶片接合之后去除或减少残留在Si-Si界面处的超薄界面氧化物的厚度的方法。 特别地，本发明提供了一种去除在亲水性Si-Si晶片接合之后残留的超薄界面氧化物以产生具有与通过疏水性接合实现的性能相当的特性的结合Si-Si界面的方法。 约2至约3nm的界面氧化物层通过高温退火（例如1300°-1330℃退火1-5小时）被溶解掉。 当粘合界面处的Si表面具有不同的表面取向时，例如当具有（100）取向的Si表面被结合到具有（110）取向的Si表面时，本发明的方法被用于最好的优点。 在本发明的更一般的方面中，类似的退火工艺可用于去除设置在两个含硅半导体材料的键合界面处的不期望的材料。 两种含硅半导体材料在表面晶体取向，微结构（单晶，多晶或无定形）和组成上可以相同或不同。

公开(公告)号：US07999251B2

公开(公告)日：2011-08-16

申请号：US11519176

申请日：2006-09-11

申请人： Jack O. Chu ,  Guy M. Cohen ,  John A. Ott ,  Michael J. Rooks ,  Paul M. Solomon

发明人： Jack O. Chu ,  Guy M. Cohen ,  John A. Ott ,  Michael J. Rooks ,  Paul M. Solomon

IPC分类号： H01L29/775 ,  H01L29/786

CPC分类号： H01L29/0665 ,  B82Y10/00 ,  H01L29/0673 ,  H01L29/458 ,  H01L29/7839 ,  H01L29/785 ,  H01L29/78618 ,  H01L29/78684 ,  H01L29/78696

摘要： A FET structure with a nanowire forming the FET channel, and doped source and drain regions formed by radial epitaxy from the nanowire body is disclosed. A top gated and a bottom gated nanowire FET structures are discussed. The source and drain fabrication can use either selective or non-selective epitaxy.

摘要翻译： 公开了具有形成FET沟道的纳米线的FET结构以及由纳米线体径向外延形成的掺杂源极和漏极区。 讨论了顶盖门控和底部门控纳米线FET结构。 源极和漏极制造可以使用选择性或非选择性外延。

公开(公告)号：US06858502B2

公开(公告)日：2005-02-22

申请号：US09989770

申请日：2001-11-20

申请人： Jack Oon Chu ,  Richard Hammond ,  Khalid EzzEldin Ismail ,  Steven John Koester ,  Patricia May Mooney ,  John A. Ott

发明人： Jack Oon Chu ,  Richard Hammond ,  Khalid EzzEldin Ismail ,  Steven John Koester ,  Patricia May Mooney ,  John A. Ott

IPC分类号： H01L29/161 ,  H01L21/338 ,  H01L29/10 ,  H01L29/778 ,  H01L29/78 ,  H01L29/812 ,  H01L21/336

CPC分类号： H01L29/7782 ,  H01L29/1025 ,  H01L29/1054

摘要： A method and a layered heterostructure for forming p-channel field effect transistors is described incorporating a plurality of semiconductor layers on a semiconductor substrate, a composite channel structure of a first epitaxial Ge layer and a second compressively strained SiGe layer having a higher barrier or a deeper confining quantum well and having extremely high hole mobility. The invention overcomes the problem of a limited hole mobility for a p-channel device with only a single compressively strained SiGe channel layer.

摘要翻译： 一种用于形成p沟道场效应晶体管的方法和分层异质结构被描述为在半导体衬底上并入多个半导体层，第一外延Ge层的复合沟道结构和具有较高势垒的第二压缩应变SiGe层 更深的约束量子阱并具有极高的空穴迁移率。 本发明克服了仅具有单个压缩应变SiGe沟道层的p沟道器件的有限空穴迁移率的问题。

公开(公告)号：US20140024211A1

公开(公告)日：2014-01-23

申请号：US13551962

申请日：2012-07-18

申请人： John A. Ott ,  Ageeth A. Bol

发明人： John A. Ott ,  Ageeth A. Bol

IPC分类号： H01L21/768

CPC分类号： H01L23/52 ,  H01L21/7682 ,  H01L21/76852 ,  H01L21/76885 ,  H01L23/5222 ,  H01L23/53238 ,  H01L23/53276 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/0001 ,  H01L2924/00

摘要： A contiguous layer of graphene is formed on exposed sidewall surfaces and a topmost surface of a copper-containing structure that is present on a surface of a substrate. The presence of the contiguous layer of graphene on the copper-containing structure reduces copper oxidation and surface diffusion of copper ions and thus improves the electromigration resistance of the structure. These benefits can be obtained using graphene without increasing the resistance of copper-containing structure.

公开(公告)号：US08610278B1

公开(公告)日：2013-12-17

申请号：US13587521

申请日：2012-08-16

申请人： John A. Ott ,  Ageeth A. Bol

发明人： John A. Ott ,  Ageeth A. Bol

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L23/52 ,  H01L21/7682 ,  H01L21/76852 ,  H01L21/76885 ,  H01L23/5222 ,  H01L23/53238 ,  H01L23/53276 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/0001 ,  H01L2924/00

摘要： A contiguous layer of graphene is formed on exposed sidewall surfaces and a topmost surface of a copper-containing structure that is present on a surface of a substrate. The presence of the contiguous layer of graphene on the copper-containing structure reduces copper oxidation and surface diffusion of copper ions and thus improves the electromigration resistance of the structure. These benefits can be obtained using graphene without increasing the resistance of copper-containing structure.

公开(公告)号：US20130302978A1

公开(公告)日：2013-11-14

申请号：US13605763

申请日：2012-09-06

申请人： Griselda Bonilla ,  Christos D. Dimitrakopoulos ,  Alfred Grill ,  James B. Hannon ,  Qinghuang Lin ,  Deborah A. Neumayer ,  Satoshi Oida ,  John A. Ott ,  Dirk Pfeiffer

发明人： Griselda Bonilla ,  Christos D. Dimitrakopoulos ,  Alfred Grill ,  James B. Hannon ,  Qinghuang Lin ,  Deborah A. Neumayer ,  Satoshi Oida ,  John A. Ott ,  Dirk Pfeiffer

IPC分类号： H01L21/768

CPC分类号： H01L21/76877 ,  H01L21/76835 ,  H01L21/76846 ,  H01L21/76849 ,  H01L21/76852 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

摘要： Interconnect structures including a graphene cap located on exposed surfaces of a copper structure are provided. In some embodiments, the graphene cap is located only atop the uppermost surface of the copper structure, while in other embodiments the graphene cap is located along vertical sidewalls and atop the uppermost surface of the copper structure. The copper structure is located within a dielectric material.

摘要翻译： 提供了包括位于铜结构的暴露表面上的石墨烯盖的互连结构。 在一些实施例中，石墨烯盖仅位于铜结构的最上表面的顶部，而在其它实施例中，石墨烯盖位于垂直侧壁和铜结构的最上表面的顶部。 铜结构位于电介质材料内。

公开(公告)号：US20130299988A1

公开(公告)日：2013-11-14

申请号：US13468693

申请日：2012-05-10

申请人： Griselda Bonilla ,  Christos D. Dimitrakopoulos ,  Alfred Grill ,  James B. Hannon ,  Qinghuang Lin ,  Deborah A. Neumayer ,  Satoshi Oida ,  John A. Ott ,  Dirk Pfeiffer

发明人： Griselda Bonilla ,  Christos D. Dimitrakopoulos ,  Alfred Grill ,  James B. Hannon ,  Qinghuang Lin ,  Deborah A. Neumayer ,  Satoshi Oida ,  John A. Ott ,  Dirk Pfeiffer

IPC分类号： H01L23/485 ,  H01L21/768

CPC分类号： H01L21/76877 ,  H01L21/76835 ,  H01L21/76846 ,  H01L21/76849 ,  H01L21/76852 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

摘要： Interconnect structures including a graphene cap located on exposed surfaces of a copper structure are provided. In some embodiments, the graphene cap is located only atop the uppermost surface of the copper structure, while in other embodiments the graphene cap is located along vertical sidewalls and atop the uppermost surface of the copper structure. The copper structure is located within a dielectric material.

摘要翻译： 提供了包括位于铜结构的暴露表面上的石墨烯盖的互连结构。 在一些实施例中，石墨烯盖仅位于铜结构的最上表面的顶部，而在其它实施例中，石墨烯盖位于垂直侧壁和铜结构的最上表面的顶部。 铜结构位于电介质材料内。