公开(公告)号：US07521376B2

公开(公告)日：2009-04-21

申请号：US11259165

申请日：2005-10-26

申请人： Martin M. Frank ,  Steven J. Koester ,  John A. Ott ,  Huiling Shang

发明人： Martin M. Frank ,  Steven J. Koester ,  John A. Ott ,  Huiling Shang

IPC分类号： H01L21/469

CPC分类号： H01L21/02052 ,  H01L21/02046 ,  H01L21/02175 ,  H01L21/0228 ,  H01L21/28255 ,  H01L21/306 ,  H01L21/31604 ,  H01L29/513 ,  H01L29/66181

摘要： A method and structure in which Ge-based semiconductor devices such as FETs and MOS capacitors can be obtained are provided. Specifically, the present invention provides a method of forming a semiconductor device including a stack including a dielectric layer and a conductive material located on and/or within a Ge-containing material (layer or wafer) in which the surface thereof is non-oxygen chalcogen rich. By providing a non-oxygen chalcogen rich interface, the formation of undesirable interfacial compounds during and after dielectric growth is suppressed and interfacial traps are reduced in density.

摘要翻译： 提供了可以获得诸如FET和MOS电容器的Ge基半导体器件的方法和结构。 具体地说，本发明提供了一种形成半导体器件的方法，该半导体器件包括一个包含电介质层和导电材料的叠层，该叠层位于其表面为非氧硫属元素的含Ge材料（层或晶片）之上和/或之内 丰富。 通过提供非氧贫硫族元素界面，抑制了电介质生长过程中和之后不希望的界面化合物的形成，并且界面陷阱的密度降低。

公开(公告)号：US09513244B2

公开(公告)日：2016-12-06

申请号：US14111753

申请日：2012-04-13

申请人： Steven J. Koester

发明人： Steven J. Koester

IPC分类号： H01L21/20 ,  G01N27/22 ,  H01L29/10 ,  H01L29/16 ,  H01L29/423 ,  H01L29/93 ,  H01L31/08 ,  H01L31/115 ,  G01R27/26

CPC分类号： G01N27/221 ,  G01N27/227 ,  G01R27/2605 ,  H01L29/1025 ,  H01L29/1606 ,  H01L29/42312 ,  H01L29/93 ,  H01L31/085 ,  H01L31/115

摘要： An electrical device includes at least one graphene quantum capacitance varactor. In some examples, the graphene quantum capacitance varactor includes an insulator layer, a graphene layer disposed on the insulator layer, a dielectric layer disposed on the graphene layer, a gate electrode formed on the dielectric layer, and at least one contact electrode disposed on the graphene layer and making electrical contact with the graphene layer. In other examples, the graphene quantum capacitance varactor includes an insulator layer, a gate electrode recessed in the insulator layer, a dielectric layer formed on the gate electrode, a graphene layer formed on the dielectric layer, wherein the graphene layer comprises an exposed surface opposite the dielectric layer, and at least one contact electrode formed on the graphene layer and making electrical contact with the graphene layer.

摘要翻译： 电气装置包括至少一个石墨烯量子电容变容二极管。 在一些示例中，石墨烯量子电容变容二极管包括绝缘体层，设置在绝缘体层上的石墨烯层，设置在石墨烯层上的电介质层，形成在电介质层上的栅极电极，以及设置在绝缘体层上的至少一个接触电极 石墨烯层，并与石墨烯层电接触。 在其他实例中，石墨烯量子电容变容二极管包括绝缘体层，凹入绝缘体层中的栅电极，形成在栅电极上的电介质层，形成在电介质层上的石墨烯层，其中石墨烯层包括相对的暴露表面 所述电介质层和形成在所述石墨烯层上并与所述石墨烯层电接触的至少一个接触电极。

公开(公告)号：US20140145735A1

公开(公告)日：2014-05-29

申请号：US14111753

申请日：2012-04-13

申请人： Steven J. Koester

发明人： Steven J. Koester

IPC分类号： G01N27/22 ,  G01R27/26

CPC分类号： G01N27/221 ,  G01N27/227 ,  G01R27/2605 ,  H01L29/1025 ,  H01L29/1606 ,  H01L29/42312 ,  H01L29/93 ,  H01L31/085 ,  H01L31/115

摘要： An electrical device includes at least one graphene quantum capacitance varactor. In some examples, the graphene quantum capacitance varactor includes an insulator layer, a graphene layer disposed on the insulator layer, a dielectric layer disposed on the graphene layer, a gate electrode formed on the dielectric layer, and at least one contact electrode disposed on the graphene layer and making electrical contact with the graphene layer. In other examples, the graphene quantum capacitance varactor includes an insulator layer, a gate electrode recessed in the insulator layer, a dielectric layer formed on the gate electrode, a graphene layer formed on the dielectric layer, wherein the graphene layer comprises an exposed surface opposite the dielectric layer, and at least one contact electrode formed on the graphene layer and making electrical contact with the graphene layer.

摘要翻译： 电气装置包括至少一个石墨烯量子电容变容二极管。 在一些示例中，石墨烯量子电容变容二极管包括绝缘体层，设置在绝缘体层上的石墨烯层，设置在石墨烯层上的电介质层，形成在电介质层上的栅电极，以及设置在绝缘体层上的至少一个接触电极 石墨烯层，并与石墨烯层电接触。 在其他实例中，石墨烯量子电容变容二极管包括绝缘体层，凹入绝缘体层中的栅电极，形成在栅电极上的电介质层，形成在电介质层上的石墨烯层，其中石墨烯层包括相对的暴露表面 所述电介质层和形成在所述石墨烯层上并与所述石墨烯层电接触的至少一个接触电极。

公开(公告)号：US08298914B2

公开(公告)日：2012-10-30

申请号：US12194198

申请日：2008-08-19

申请人： Mukta G. Farooq ,  Robert Hannon ,  Subramanian S. Iyer ,  Steven J. Koester ,  Fei Liu ,  Sampath Purushothaman ,  Albert M. Young ,  Roy R. Yu

发明人： Mukta G. Farooq ,  Robert Hannon ,  Subramanian S. Iyer ,  Steven J. Koester ,  Fei Liu ,  Sampath Purushothaman ,  Albert M. Young ,  Roy R. Yu

IPC分类号： H01L21/4763

CPC分类号： H01L25/0657 ,  H01L21/6835 ,  H01L25/18 ,  H01L25/50 ,  H01L2221/68377 ,  H01L2224/0401 ,  H01L2224/05001 ,  H01L2224/05008 ,  H01L2224/05009 ,  H01L2224/05024 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05558 ,  H01L2224/05568 ,  H01L2224/0557 ,  H01L2224/056 ,  H01L2224/131 ,  H01L2224/16227 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/33181 ,  H01L2224/73153 ,  H01L2224/73253 ,  H01L2224/83121 ,  H01L2224/83895 ,  H01L2224/92242 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06593 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/1431 ,  H01L2924/1433 ,  H01L2924/1434 ,  H01L2924/1436 ,  H01L2924/1437 ,  H01L2924/15311 ,  H01L2924/157 ,  H01L2924/37001 ,  H01L2224/83 ,  H01L2224/11 ,  H01L2924/014 ,  H01L2924/00014

摘要： A method is provided for fabricating a 3D integrated circuit structure. Provided are an interface wafer including a first wiring layer and through-silicon vias, and a first active circuitry layer wafer including active circuitry. The first active circuitry layer wafer is bonded to the interface wafer. Then, a first portion of the first active circuitry layer wafer is removed such that a second portion remains attached to the interface wafer. A stack structure including the interface wafer and the second portion of the first active circuitry layer wafer is bonded to a base wafer. Next, the interface wafer is thinned so as to form an interface layer, and metallizations coupled through the through-silicon vias in the interface layer to the first wiring layer are formed on the interface layer. Also provided is a tangible computer readable medium encoded with a program that comprises instructions for performing such a method.

摘要翻译： 提供了一种用于制造3D集成电路结构的方法。 提供了包括第一布线层和穿硅通孔的接口晶片，以及包括有源电路的第一有源电路层晶片。 第一有源电路层晶片被结合到界面晶片。 然后，去除第一有源电路层晶片的第一部分，使得第二部分保持附着到界面晶片。 包括接口晶片和第一有源电路层晶片的第二部分的堆叠结构被结合到基底晶片。 接下来，将界面晶片减薄以形成界面层，并且在界面层上形成通过界面层中的穿硅通孔耦合到第一布线层的金属化。 还提供了一种用包括用于执行这种方法的指令的程序编码的有形计算机可读介质。

公开(公告)号：US20120118383A1

公开(公告)日：2012-05-17

申请号：US12946216

申请日：2010-11-15

申请人： Stephen W. Bedell ,  Norma E. Sosa Cortes ,  Wilfried E. Haensch ,  Steven J. Koester ,  Devendra K. Sadana ,  Katherine L. Saenger ,  Ghavam Shahidi ,  Davood Shahrjerdi

发明人： Stephen W. Bedell ,  Norma E. Sosa Cortes ,  Wilfried E. Haensch ,  Steven J. Koester ,  Devendra K. Sadana ,  Katherine L. Saenger ,  Ghavam Shahidi ,  Davood Shahrjerdi

IPC分类号： H01L31/0264 ,  H01L31/18

CPC分类号： H01L27/142 ,  H01L31/02008 ,  H01L31/0747 ,  H01L31/075 ,  H01L31/076 ,  H01L31/078 ,  H01L31/1804 ,  H01L31/202 ,  Y02E10/547 ,  Y02E10/548 ,  Y02P70/521

摘要： An autonomous integrated circuit (IC) includes a solar cell formed on a bottom substrate of a silicon-on-insulator (SOI) substrate as a handle substrate; an insulating layer of the SOI substrate located on top of the solar cell; and a device layer formed on a top semiconductor layer of the SOI substrate located on top of the insulating layer, wherein a top contact of the device layer is electrically connected to a bottom contact of the solar cell such that the solar cell is enabled to power the device layer.

摘要翻译： 自主集成电路（IC）包括形成在作为处理衬底的绝缘体上硅（SOI）衬底的底部衬底上的太阳能电池; 位于太阳能电池顶部的SOI衬底的绝缘层; 以及形成在位于绝缘层顶部的SOI衬底的顶部半导体层上的器件层，其中器件层的顶部接触电连接到太阳能电池的底部接触，使得太阳能电池能够通电 设备层。

公开(公告)号：US08129256B2

公开(公告)日：2012-03-06

申请号：US12194065

申请日：2008-08-19

申请人： Mukta G. Farooq ,  Robert Hannon ,  Subramanian S. Iyer ,  Steven J. Koester ,  Sampath Purushothaman ,  Roy R. Yu

发明人： Mukta G. Farooq ,  Robert Hannon ,  Subramanian S. Iyer ,  Steven J. Koester ,  Sampath Purushothaman ,  Roy R. Yu

IPC分类号： H01L21/30

CPC分类号： H01L27/105 ,  H01L24/11 ,  H01L27/0688 ,  H01L2224/05008 ,  H01L2224/05009 ,  H01L2224/05024 ,  H01L2224/05147 ,  H01L2224/05184 ,  H01L2224/05568 ,  H01L2224/0557 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/00 ,  H01L2224/05599

摘要： A method is provided for fabricating a 3D integrated circuit structure. According to the method, a first active circuitry layer wafer is provided. The first active circuitry layer wafer comprises a P+ portion covered by a P− layer, and the P− layer includes active circuitry. The first active circuitry layer wafer is bonded face down to an interface wafer that includes a first wiring layer, and then the P+ portion of the first active circuitry layer wafer is selectively removed with respect to the P− layer of the first active circuitry layer wafer. Next, a wiring layer is fabricated on the backside of the P− layer. Also provided are a tangible computer readable medium encoded with a program for fabricating a 3D integrated circuit structure, and a 3D integrated circuit structure.

摘要翻译： 提供了一种用于制造3D集成电路结构的方法。 根据该方法，提供第一有源电路层晶片。 第一有源电路层晶片包括由P层覆盖的P +部分，并且P层包括有源电路。 第一有源电路层晶片面向下接合到包括第一布线层的接口晶片，然后相对于第一有源电路层晶片的P层选择性地去除第一有源电路层晶片的P +部分 。 接下来，在P-层的背面上制造布线层。 还提供了用用于制造3D集成电路结构的程序编码的有形计算机可读介质和3D集成电路结构。

公开(公告)号：US20110193169A1

公开(公告)日：2011-08-11

申请号：US13088339

申请日：2011-04-16

申请人： Solomon Assefa ,  Kuan-Neng Chen ,  Steven J. Koester ,  Yurii A. Vlasov

发明人： Solomon Assefa ,  Kuan-Neng Chen ,  Steven J. Koester ,  Yurii A. Vlasov

IPC分类号： H01L27/12

CPC分类号： H01L27/0688

摘要： Integrated circuits having complementary metal-oxide semiconductor (CMOS) and photonics circuitry and techniques for three-dimensional integration thereof are provided. In one aspect, a three-dimensional integrated circuit comprises a bottom device layer and a top device layer. The bottom device layer comprises a digital CMOS circuitry layer; and a first bonding oxide layer adjacent to the digital CMOS circuitry layer. The top device layer comprises a substrate; an analog CMOS and photonics circuitry layer formed in a silicon-on-insulator (SOI) layer adjacent to the substrate, the SOI layer having a buried oxide (BOX) with a thickness of greater than or equal to about one micrometer; and a second bonding oxide layer adjacent to a side of the analog CMOS and photonics circuitry layer opposite the substrate. The bottom device layer is bonded to the top device layer by an oxide-to-oxide bond between the first bonding oxide layer and the second bonding oxide layer.

摘要翻译： 提供了具有互补金属氧化物半导体（CMOS）的集成电路和用于其三维集成的光子电路和技术。 一方面，三维集成电路包括底部器件层和顶部器件层。 底部器件层包括数字CMOS电路层; 以及与数字CMOS电路层相邻的第一结合氧化物层。 顶部器件层包括衬底; 形成在与衬底相邻的绝缘体上硅（SOI）层中的模拟CMOS和光子电路层，所述SOI层具有厚度大于或等于约1微米的掩埋氧化物（BOX）; 以及与模拟CMOS和与衬底相对的光子电路层的一侧相邻的第二结合氧化物层。 底部器件层通过第一接合氧化物层和第二接合氧化物层之间的氧化物 - 氧化物键接合到顶部器件层。

公开(公告)号：US07964896B2

公开(公告)日：2011-06-21

申请号：US12180927

申请日：2008-07-28

申请人： Edward W. Kiewra ,  Steven J. Koester ,  Devendra K. Sadana ,  Ghavam Shahidi ,  Yanning Sun

发明人： Edward W. Kiewra ,  Steven J. Koester ,  Devendra K. Sadana ,  Ghavam Shahidi ,  Yanning Sun

IPC分类号： H01L29/66

CPC分类号： H01L29/7787 ,  H01L29/66462

摘要： A semiconductor-containing heterostructure including, from bottom to top, a III-V compound semiconductor buffer layer, a III-V compound semiconductor channel layer, a III-V compound semiconductor barrier layer, and an optional, yet preferred, III-V compound semiconductor cap layer is provided. The barrier layer may be doped, or preferably undoped. The III-V compound semiconductor buffer layer and the III-V compound semiconductor barrier layer are comprised of materials that have a wider band gap than that of the III-V compound semiconductor channel layer. Since wide band gap materials are used for the buffer and barrier layer and a narrow band gap material is used for the channel layer, carriers are confined to the channel layer under certain gate bias range. The inventive heterostructure can be employed as a buried channel structure in a field effect transistor.

摘要翻译： 一种含半导体的异质结构，包括III-V族化合物半导体缓冲层，III-V族化合物半导体沟道层，III-V族化合物半导体阻挡层和任选的，但优选的III-V族化合物 提供半导体盖层。 阻挡层可以是掺杂的，或者优选地是未掺杂的。 III-V族化合物半导体缓冲层和III-V族化合物半导体阻挡层由具有比III-V化合物半导体沟道层宽的带隙的材料构成。 由于宽带隙材料用于缓冲层和阻挡层，并且窄带隙材料用于沟道层，所以载流子在特定栅极偏置范围内被限制在沟道层。 本发明的异质结构可以用作场效应晶体管中的掩埋沟道结构。

公开(公告)号：US20110012202A1

公开(公告)日：2011-01-20

申请号：US12505824

申请日：2009-07-20

申请人： Josephine B. Chang ,  Leland Chang ,  Steven J. Koester ,  Jeffrey W. Sleight

发明人： Josephine B. Chang ,  Leland Chang ,  Steven J. Koester ,  Jeffrey W. Sleight

IPC分类号： H01L27/11 ,  H01L21/8244

CPC分类号： H01L27/088 ,  H01L21/845 ,  H01L27/11 ,  H01L27/1104 ,  H01L27/1108 ,  H01L27/1207 ,  H01L27/1211 ,  H01L29/7841

摘要： A memory cell has N≧6 transistors, in which two are access transistors, at least one pair [say (N−2)/2] are pull-up transistors, and at least another pair [say (N−2)/2] are pull-down transistors. The pull-up and pull-down transistors are all coupled between the two access transistors. Each of the access transistors and the pull-up transistors are the same type, p-type or n-type. Each of the pull-down transistors is the other type, p-type or n-type. The access transistors are floating body devices. The pull-down transistors are non-floating body devices. The pull-up transistors may be floating or non-floating body devices. Various specific implementations and methods of making the memory cell are also detailed.

公开(公告)号：US20080185618A1

公开(公告)日：2008-08-07

申请号：US11556755

申请日：2006-11-06

申请人： Jack O. Chu ,  Gabriel K. Dehlinger ,  Alfred Grill ,  Steven J. Koester ,  Qiqing Ouyang ,  Jeremy D. Schaub

发明人： Jack O. Chu ,  Gabriel K. Dehlinger ,  Alfred Grill ,  Steven J. Koester ,  Qiqing Ouyang ,  Jeremy D. Schaub

IPC分类号： H01L27/146

CPC分类号： H01L31/101

摘要： The invention addresses the problem of creating a high-speed, high-efficiency photodetector that is compatible with Si CMOS technology. The structure consists of a Ge absorbing layer on a thin SOI substrate, and utilizes isolation regions, alternating n- and p-type contacts, and low-resistance surface electrodes. The device achieves high bandwidth by utilizing a buried insulating layer to isolate carriers generated in the underlying substrate, high quantum efficiency over a broad spectrum by utilizing a Ge absorbing layer, low voltage operation by utilizing thin a absorbing layer and narrow electrode spacings, and compatibility with CMOS devices by virtue of its planar structure and use of a group IV absorbing material. The method for fabricating the photodetector uses direct growth of Ge on thin SOI or an epitaxial oxide, and subsequent thermal annealing to achieve a high-quality absorbing layer. This method limits the amount of Si available for interdiffusion, thereby allowing the Ge layer to be annealed without causing substantial dilution of the Ge layer by the underlying Si.

摘要翻译： 本发明解决了与Si CMOS技术兼容的高速高效光电探测器的问题。 该结构由薄的SOI衬底上的Ge吸收层组成，并且使用隔离区，交替的n型和p型接触以及低电阻表面电极。 该器件通过利用掩埋绝缘层来隔离衬底中产生的载流子，通过利用Ge吸收层，在广谱上产生高量子效率，利用薄吸收层和窄电极间隔的低电压操作以及兼容性来实现高带宽 通过其平面结构和使用IV族吸收材料的CMOS器件。 用于制造光电检测器的方法使用在薄SOI或外延氧化物上的Ge的直接生长，以及随后的热退火以实现高质量的吸收层。 该方法限制可用于相互扩散的Si的量，从而允许Ge层退火，而不会导致Ge层被下面的Si大量稀释。