公开(公告)号：US07521376B2

公开(公告)日：2009-04-21

申请号：US11259165

申请日：2005-10-26

申请人： Martin M. Frank ,  Steven J. Koester ,  John A. Ott ,  Huiling Shang

发明人： Martin M. Frank ,  Steven J. Koester ,  John A. Ott ,  Huiling Shang

IPC分类号： H01L21/469

CPC分类号： H01L21/02052 ,  H01L21/02046 ,  H01L21/02175 ,  H01L21/0228 ,  H01L21/28255 ,  H01L21/306 ,  H01L21/31604 ,  H01L29/513 ,  H01L29/66181

摘要： A method and structure in which Ge-based semiconductor devices such as FETs and MOS capacitors can be obtained are provided. Specifically, the present invention provides a method of forming a semiconductor device including a stack including a dielectric layer and a conductive material located on and/or within a Ge-containing material (layer or wafer) in which the surface thereof is non-oxygen chalcogen rich. By providing a non-oxygen chalcogen rich interface, the formation of undesirable interfacial compounds during and after dielectric growth is suppressed and interfacial traps are reduced in density.

摘要翻译： 提供了可以获得诸如FET和MOS电容器的Ge基半导体器件的方法和结构。 具体地说，本发明提供了一种形成半导体器件的方法，该半导体器件包括一个包含电介质层和导电材料的叠层，该叠层位于其表面为非氧硫属元素的含Ge材料（层或晶片）之上和/或之内 丰富。 通过提供非氧贫硫族元素界面，抑制了电介质生长过程中和之后不希望的界面化合物的形成，并且界面陷阱的密度降低。

公开(公告)号：US08941169B2

公开(公告)日：2015-01-27

申请号：US13550102

申请日：2012-07-16

申请人： Martin M. Frank

发明人： Martin M. Frank

IPC分类号： H01L29/788 ,  H01L21/28 ,  H01L27/115

CPC分类号： H01L21/28273 ,  H01L27/11521

摘要： A floating gate device is provided. A tunnel oxide layer is formed over the channel. A floating gate is formed over the tunnel oxide layer. A high-k dielectric layer is formed over the floating gate. A control gate is formed over the high-k dielectric layer. At least one of the control gate and/or the floating gate includes an oxygen scavenging element. The oxygen scavenging element is configured to decrease an oxygen density at least one of at a first interface between the control gate and the high-k dielectric layer, at a second interface between the high-k dielectric layer and the floating gate, at a third interface between the floating gate and the tunnel oxide layer, and at a fourth interface between the tunnel oxide layer and the channel responsive to annealing.

摘要翻译： 提供浮动门装置。 在通道上形成隧道氧化物层。 在隧道氧化物层上形成浮栅。 在浮栅上形成高k电介质层。 在高k电介质层上形成控制栅极。 控制栅极和/或浮动栅极中的至少一个包括氧气清除元件。 氧清除元件被配置为在第k个高k介电层和浮动栅极之间的第二界面处，在第三个控制栅极和高k电介质层之间的第一界面处的至少一个处降低氧气密度 界面在浮动栅极和隧道氧化物层之间，并且在隧道氧化物层和沟道之间的第四界面响应于退火。

公开(公告)号：US08674456B2

公开(公告)日：2014-03-18

申请号：US13442090

申请日：2012-04-09

申请人： Martin M. Frank

发明人： Martin M. Frank

IPC分类号： H01L29/66 ,  H01L27/12 ,  H01L21/02

CPC分类号： H01L21/28247 ,  H01L21/2807 ,  H01L21/28079 ,  H01L21/28088 ,  H01L21/28176 ,  H01L21/3105 ,  H01L21/326 ,  H01L21/823842 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/517

摘要： An apparatus includes a wafer annealing tool and a plurality of electrodes coupled to the wafer annealing tool, wherein the electrodes are configured to be in physical contact with a wafer so that, when the wafer is annealed, a negative electrical bias is formed across one or more gate stacks of the wafer.

摘要翻译： 一种设备包括晶片退火工具和耦合到晶片退火工具的多个电极，其中电极被配置为与晶片物理接触，使得当晶片退火时，负电偏压跨越一个或 更多的晶片堆叠。

公开(公告)号：US08559217B2

公开(公告)日：2013-10-15

申请号：US12964980

申请日：2010-12-10

申请人： Catherine A. Dubourdieu ,  Martin M. Frank ,  Bipin Rajendran ,  Alejandro G. Schrott

发明人： Catherine A. Dubourdieu ,  Martin M. Frank ,  Bipin Rajendran ,  Alejandro G. Schrott

IPC分类号： G11C11/00

CPC分类号： H01L45/1608 ,  G11C11/22 ,  G11C13/0004 ,  G11C13/0069 ,  G11C2013/0095 ,  H01L45/06 ,  H01L45/12 ,  H01L45/1233 ,  H01L45/143 ,  H01L45/144

摘要： An example embodiment disclosed is a phase change memory cell. The memory cell includes a phase change material and a transducer positioned proximate the phase change material. The phase change material is switchable between at least an amorphous state and a crystalline state. The transducer is configured to activate when the phase change material is changed from the amorphous state to the crystalline state. In a particular embodiment, the transducer is ferroelectric material.

摘要翻译： 所公开的示例实施例是相变存储单元。 存储单元包括相变材料和位于相变材料附近的换能器。 相变材料可在至少非晶状态和结晶状态之间切换。 换能器被配置为当相变材料从非晶状态转变为结晶状态时激活。 在特定实施例中，换能器是铁电材料。

公开(公告)号：US08420474B1

公开(公告)日：2013-04-16

申请号：US13348355

申请日：2012-01-11

申请人： Martin M. Frank ,  Dechao Guo ,  Shu-Jen Hen ,  Kuen-Ting Shiu

发明人： Martin M. Frank ,  Dechao Guo ,  Shu-Jen Hen ,  Kuen-Ting Shiu

IPC分类号： H01L21/8238

CPC分类号： H01L51/0048 ,  B82Y10/00 ,  H01L21/823807 ,  H01L21/823828 ,  H01L27/1203 ,  H01L29/413 ,  H01L51/0558

摘要： A field effect transistor fabrication method includes defining a gate structure on a substrate, depositing a dielectric layer on the gate structure, depositing a first metal layer on the dielectric layer, removing a portion of the first metal layer, depositing a second metal layer, annealing the first and second metal layers, and defining a carbon based device on the dielectric layer and the gate structure.

公开(公告)号：US20120292677A1

公开(公告)日：2012-11-22

申请号：US13108340

申请日：2011-05-16

申请人： Catherine A. Dubourdieu ,  David J. Frank ,  Martin M. Frank ,  Vijay Narayanan ,  Paul M. Solomon ,  Thomas N. Theis

发明人： Catherine A. Dubourdieu ,  David J. Frank ,  Martin M. Frank ,  Vijay Narayanan ,  Paul M. Solomon ,  Thomas N. Theis

IPC分类号： H01L29/772

CPC分类号： H01L29/4232 ,  H01L29/42316 ,  H01L29/812

摘要： Ferroelectric semiconductor switching devices are provided, including field effect transistor (FET) devices having gate stack structures formed with a ferroelectric layer disposed between a gate contact and a thin conductive layer (“quantum conductive layer”) . The gate contact and ferroelectric layer serve to modulate an effective work function of the thin conductive layer. The thin conductive layer with the modulated work function is coupled to a semiconductor channel layer to modulate current flow through the semiconductor and achieve a steep sub-threshold slope.

摘要翻译： 提供了铁电半导体开关器件，包括具有栅极叠层结构的场效应晶体管（FET）器件，栅极堆叠结构形成有设置在栅极接触和薄导电层（量子导电层）之间的铁电层。 栅极接触和铁电层用于调制薄导电层的有效功函数。 具有调制功函数的薄导电层耦合到半导体沟道层，以调制通过半导体的电流，并实现陡峭的子阈值斜率。

公开(公告)号：US08304306B2

公开(公告)日：2012-11-06

申请号：US13073110

申请日：2011-03-28

申请人： Jin Cai ,  Eduard A. Cartier ,  Martin M. Frank ,  Marwan H. Khater

发明人： Jin Cai ,  Eduard A. Cartier ,  Martin M. Frank ,  Marwan H. Khater

IPC分类号： H01L21/8238

CPC分类号： H01L21/823468 ,  H01L21/28176 ,  H01L21/28247 ,  H01L21/823462 ,  H01L21/823857 ,  H01L21/823864 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/6653 ,  H01L29/78

摘要： A method for forming a semiconductor device includes forming a first field effect transistor (FET) and a second FET on a substrate, the first FET comprising a first interfacial oxide layer, and the second FET comprising a second interfacial oxide layer; encapsulating the first interfacial oxide layer of the first FET; and performing lateral oxidation of the second interfacial oxide layer of the second FET, wherein the lateral oxidation of the second interfacial oxide layer of the second FET converts a portion of the substrate located underneath the second FET into additional interfacial oxide.

摘要翻译： 一种用于形成半导体器件的方法包括在衬底上形成第一场效应晶体管（FET）和第二FET，所述第一FET包括第一界面氧化物层，所述第二FET包括第二界面氧化物层; 封装第一FET的第一界面氧化物层; 以及执行第二FET的第二界面氧化物层的侧向氧化，其中第二FET的第二界面氧化物层的侧向氧化将位于第二FET下面的衬底的一部分转换为另外的界面氧化物。

公开(公告)号：US08212322B2

公开(公告)日：2012-07-03

申请号：US12720354

申请日：2010-03-09

申请人： Martin M. Frank ,  Arvind Kumar ,  Vijay Narayanan ,  Vamsi K. Paruchuri ,  Jeffrey Sleight

发明人： Martin M. Frank ,  Arvind Kumar ,  Vijay Narayanan ,  Vamsi K. Paruchuri ,  Jeffrey Sleight

IPC分类号： H01L21/8234 ,  H01L21/8244

CPC分类号： H01L27/1104 ,  H01L27/11 ,  H01L27/1108

摘要： Techniques for combining transistors having different threshold voltage requirements from one another are provided. In one aspect, a semiconductor device comprises a substrate having a first and a second nFET region, and a first and a second pFET region; a logic nFET on the substrate over the first nFET region; a logic pFET on the substrate over the first pFET region; a SRAM nFET on the substrate over the second nFET region; and a SRAM pFET on the substrate over the second pFET region, each comprising a gate stack having a metal layer over a high-K layer. The logic nFET gate stack further comprises a capping layer separating the metal layer from the high-K layer, wherein the capping layer is further configured to shift a threshold voltage of the logic nFET relative to a threshold voltage of one or more of the logic pFET, SRAM nFET and SRAM pFET.

摘要翻译： 提供了用于组合彼此具有不同阈值电压要求的晶体管的技术。 在一个方面，一种半导体器件包括具有第一和第二nFET区的衬底以及第一和第二pFET区; 在第一nFET区域上的衬底上的逻辑nFET; 在第一pFET区上的衬底上的逻辑pFET; 位于第二nFET区上的衬底上的SRAM nFET; 以及在第二pFET区上的衬底上的SRAM pFET，每个包括在高K层上具有金属层的栅极堆叠。 逻辑nFET栅极堆叠还包括将金属层与高K层分隔开的覆盖层，其中封盖层还被配置为相对于逻辑pFET中的一个或多个的阈值电压移动逻辑nFET的阈值电压 ，SRAM nFET和SRAM pFET。

公开(公告)号：US08193051B2

公开(公告)日：2012-06-05

申请号：US13047172

申请日：2011-03-14

申请人： Nestor A. Bojarczuk, Jr. ,  Cyril Cabral, Jr. ,  Eduard A. Cartier ,  Matthew W. Copel ,  Martin M. Frank ,  Evgeni P. Gousev ,  Supratik Guha ,  Rajarao Jammy ,  Vijay Narayanan ,  Vamsi K. Paruchuri

发明人： Nestor A. Bojarczuk, Jr. ,  Cyril Cabral, Jr. ,  Eduard A. Cartier ,  Matthew W. Copel ,  Martin M. Frank ,  Evgeni P. Gousev ,  Supratik Guha ,  Rajarao Jammy ,  Vijay Narayanan ,  Vamsi K. Paruchuri

IPC分类号： H01L21/8238

CPC分类号： H01L29/513 ,  H01L21/28079 ,  H01L21/28088 ,  H01L21/823857 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/517

摘要： The present invention provides a semiconductor structure including a semiconductor substrate having a plurality of source and drain diffusion regions located therein, each pair of source and drain diffusion regions are separated by a device channel. The structure further includes a first gate stack of pFET device located on top of some of the device channels, the first gate stack including a high-k gate dielectric, an insulating interlayer abutting the gate dielectric and a fully silicided metal gate electrode abutting the insulating interlayer, the insulating interlayer includes an insulating metal nitride that stabilizes threshold voltage and flatband voltage of the p-FET device to a targeted value and is one of aluminum oxynitride, boron nitride, boron oxynitride, gallium nitride, gallium oxynitride, indium nitride and indium oxynitride. A second gate stack of an nFET devices is located on top remaining device channels, the second gate stack including a high-k gate dielectric and a fully silicided gate electrode located directly atop the high-k gate dielectric.

摘要翻译： 本发明提供一种半导体结构，其包括具有位于其中的多个源极和漏极扩散区域的半导体衬底，每对源极和漏极扩散区域由器件沟道分离。 该结构还包括位于一些器件通道顶部的pFET器件的第一栅极堆叠，第一栅极堆叠包括高k栅极电介质，邻接栅极电介质的绝缘夹层和邻接绝缘体的完全硅化金属栅电极 中间层，绝缘中间层包括将p-FET器件的阈值电压和扁平带电压稳定到目标值的绝缘金属氮化物，并且是氮氧化铝，氮化硼，氮氧化硼，氮化镓，氮氧化镓，氮化铟和铟中的一种 氮氧化物。 nFET器件的第二栅极堆叠位于顶部剩余器件沟道上，第二栅极堆叠包括高k栅极电介质和直接位于高k栅极电介质顶部的完全硅化栅电极。

公开(公告)号：US07989902B2

公开(公告)日：2011-08-02

申请号：US12487248

申请日：2009-06-18

申请人： Takashi Ando ,  Changhwan Choi ,  Martin M. Frank ,  Vijay Narayanan

发明人： Takashi Ando ,  Changhwan Choi ,  Martin M. Frank ,  Vijay Narayanan

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L21/28088 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/518 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/7833

摘要： A stack of a high-k gate dielectric and a metal gate structure includes a lower metal layer, a scavenging metal layer, and an upper metal layer. The scavenging metal layer meets the following two criteria 1) a metal (M) for which the Gibbs free energy change of the reaction Si+2/y MxOy→2x/y M+SiO2 is positive 2) a metal that has a more negative Gibbs free energy per oxygen atom for formation of oxide than the material of the lower metal layer and the material of the upper metal layer. The scavenging metal layer meeting these criteria captures oxygen atoms as the oxygen atoms diffuse through the gate electrode toward the high-k gate dielectric. In addition, the scavenging metal layer remotely reduces the thickness of a silicon oxide interfacial layer underneath the high-k dielectric. As a result, the equivalent oxide thickness (EOT) of the total gate dielectric is reduced and the field effect transistor maintains a constant threshold voltage even after high temperature processes during CMOS integration.

摘要翻译： 高k栅极电介质和金属栅极结构的堆叠包括下部金属层，清除金属层和上部金属层。 清除金属层满足以下两个标准：1）反应Si + 2 / y MxOy→2x / y M + SiO2的吉布斯自由能变化为正的金属（M）2）具有更负的金属 每个氧原子吉布斯自由能用于形成氧化物，而不是下金属层的材料和上金属层的材料。 符合这些标准的清除金属层随着氧原子通过栅电极向高k栅极电介质扩散而捕获氧原子。 此外，清除金属层远远地降低了高k电介质下面的氧化硅界面层的厚度。 结果，即使在CMOS积分期间的高温处理之后，总栅极电介质的等效氧化物厚度（EOT）减小，并且场效应晶体管保持恒定的阈值电压。