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152 条记录 (耗时 0.028 秒)

    Developing apparatus, image formation apparatus, and process cartridge
    1.
    发明授权
    Developing apparatus, image formation apparatus, and process cartridge 有权
    显影装置，图像形成装置和处理盒

    公开(公告)号：US06687474B2

    公开(公告)日：2004-02-03

    申请号：US10163990

    申请日：2002-06-07

    申请人： Masahiko Yamada ,  Kentaroh Matsumoto ,  Hiroyuki Nagashima ,  Tokuya Ohjimi

    发明人： Masahiko Yamada ,  Kentaroh Matsumoto ,  Hiroyuki Nagashima ,  Tokuya Ohjimi

    IPC分类号： G03G1508

    CPC分类号： G03G15/0887 ,  G03G15/0877 ,  G03G2215/0875 ,  G03G2221/1633 ,  G03G2221/183

    摘要： A developing apparatus, an image formation apparatus and a process cartridge is provided. Even though the sealing materials of the initial developer container are stripped off in such a way that the process cartridge having the developing apparatus is tilted, the initial developer can be uniformly supplied along the central axis line of the developer carrier. The developing apparatus performs a self toner control and has an initial developer case 10 for containing the non-used initial developer 3c that is input into the developer containing space S. The initial developer case 10 is divided internally into a plurality of partition spaces 10b along the direction of the central axial line D of the developing sleeve 4, so that a plurality of partitions 10c is formed inside the initial developer case 10. Based on the opening 10a for inputting the initial developer, the partition surface F facing to the partition space 10b of each partition 10c is tilted from an imaginary plane G perpendicular to the central axial line D of the developing sleeve 4 toward one end H along the direction of the central axial line D of the developing sleeve 4.

    摘要翻译： 提供了显影装置，图像形成装置和处理盒。 即使初始显影剂容器的密封材料被剥离，使得具有显影装置的处理盒倾斜，初始显影剂可以沿显影剂载体的中心轴线均匀地供应。 显影装置执行自调色剂控制，并且具有用于容纳输入到显影剂容纳空间S中的未使用的初始显影剂3c的初始显影剂盒10.初始显影剂盒10被内部划分成多个分隔空间10b 显影套筒4的中心轴线D的方向，使得在初始显影剂盒10内部形成有多个隔板10c。基于用于输入初始显影剂的开口10a，面向分隔空间的分隔面F 每个分隔件10c的10b从垂直于显影套筒4的中心轴线D的假想平面G沿着显影套筒4的中心轴线D的方向向着一端H倾斜。

    Memory system
    8.
    发明授权
    Memory system 有权
    内存系统

    公开(公告)号：US08755233B2

    公开(公告)日：2014-06-17

    申请号：US13240014

    申请日：2011-09-22

    申请人： Hiroyuki Nagashima

    发明人： Hiroyuki Nagashima

    IPC分类号： G11C16/26 ,  G11C16/34 ,  G11C16/14 ,  G11C11/56

    CPC分类号： G11C16/12 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/14 ,  G11C16/26 ,  G11C16/3445 ,  G11C16/3454 ,  G11C16/3459 ,  G11C16/349 ,  G11C16/3495

    摘要： According to one embodiment, there is provided memory system including a non-volatile memory device, a monitoring unit, and a changing unit. The non-volatile memory device stores data. The monitoring unit monitors a characteristic of the non-volatile memory device when writing and erasing processes are performed to write and erase the data to and from the non-volatile memory device. The changing unit changes at least one of a value of a writing start voltage and an increase width of a writing voltage in the writing process in accordance with the monitored characteristic so that a time for the writing process is substantially identical to a target value. The writing process is a process in which a writing operation and a verification operation are alternately repeated.

    摘要翻译： 根据一个实施例，提供了包括非易失性存储器件，监视单元和改变单元的存储器系统。 非易失性存储器件存储数据。 当执行写入和擦除处理时，监视单元监视非易失性存储器件的特性，以向非易失性存储器件写入和擦除数据。 改变单元根据所监视的特性改变写入开始电压的值和写入电压的增加宽度中的至少一个，使得写入处理的时间与目标值基本相同。 写入处理是交替重复写入操作和验证操作的处理。

    Nonvolatile semiconductor memory device
    9.
    发明授权
    Nonvolatile semiconductor memory device 有权
    非易失性半导体存储器件

    公开(公告)号：US08575590B2

    公开(公告)日：2013-11-05

    申请号：US13038771

    申请日：2011-03-02

    申请人： Koichi Muraoka ,  Hiroyuki Nagashima

    发明人： Koichi Muraoka ,  Hiroyuki Nagashima

    IPC分类号： H01L47/00 ,  H01L27/10 ,  H01L29/06

    CPC分类号： G11C13/003 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0014 ,  G11C2213/31 ,  G11C2213/32 ,  G11C2213/56 ,  G11C2213/71 ,  G11C2213/76 ,  H01L27/101 ,  H01L27/2418 ,  H01L27/2463

    摘要： According to one embodiment, there is provided a nonvolatile semiconductor memory device including a first interconnection layer, memory cell modules each of which is formed by laminating a non-ohmic element layer with an MIM structure having an insulating film sandwiched between metal films and a variable resistance element layer, and a second interconnection layer formed on the memory cell modules, the insulating film of the non-ohmic element layer includes plural layers whose electron barriers and dielectric constants are different, or contains impurity atoms that form defect levels in the insulating film or contains semiconductor or metal dots. The nonvolatile semiconductor memory device using non-ohmic elements and variable resistance elements in which memory cells can be miniaturized and formed at low temperatures is realized by utilizing the above structures.

    摘要翻译： 根据一个实施例，提供了一种非易失性半导体存储器件，其包括第一互连层，存储单元模块，每个存储单元模块通过层叠具有MIM结构的非欧姆元件层而形成，所述MIM结构具有夹在金属膜之间的绝缘膜和可变 电阻元件层和形成在存储单元模块上的第二互连层，非欧姆元件层的绝缘膜包括其电子势垒和介电常数不同的多个层，或包含在绝缘膜中形成缺陷水平的杂质原子 或包含半导体或金属点。 通过利用上述结构，实现了使用非欧姆元件和可变电阻元件的非易失性半导体存储器件，其中存储单元可以在低温下小型化并形成。

    Semiconductor memory device
    10.
    发明授权
    Semiconductor memory device 有权
    半导体存储器件

    公开(公告)号：US08441040B2

    公开(公告)日：2013-05-14

    申请号：US12886090

    申请日：2010-09-20

    申请人： Yoichi Minemura ,  Hiroyuki Nagashima

    发明人： Yoichi Minemura ,  Hiroyuki Nagashima

    IPC分类号： H01L23/52

    CPC分类号： H01L27/2481 ,  H01L27/0688 ,  H01L27/2409 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/147

    摘要： A semiconductor memory device according to an embodiment includes: a cell array block having, above a semiconductor substrate, a plurality of first and second wirings intersecting with one another, and a plurality of memory cells, the first and second wirings being separately formed in a plurality of layers in a perpendicular direction to the semiconductor substrate; and a first via wiring, connecting the first wiring in an n1-th layer of the cell array block with the first wiring in an n2-th layer, the semiconductor substrate or another metal wiring, and extending in a laminating direction of the cell array block. The first via wiring has a cross section orthogonal to the laminating direction of the cell array block. The cross section has an elliptical shape and a longer diameter in a direction perpendicular to the first wiring direction.

    摘要翻译： 根据实施例的半导体存储器件包括：单元阵列块，其在半导体衬底上方具有彼此相交的多个第一和第二布线，以及多个存储单元，所述第一和第二布线分别形成在 在与半导体衬底垂直的方向上的多个层; 以及第一通孔布线，将第一电极阵列块的第n1层中的第一布线与第n2层的第一布线，半导体基板或其他金属布线连接，并且在电池阵列的层叠方向上延伸 块。 第一通孔布线具有与单元阵列块的层叠方向正交的截面。 横截面在垂直于第一布线方向的方向上具有椭圆形状和较长直径。