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81 条记录 (耗时 0.025 秒)

    Bipolar-MOS IC with internal voltage generator and LSI device with internal voltage generator
    1.
    发明授权
    Bipolar-MOS IC with internal voltage generator and LSI device with internal voltage generator 失效
    具有内部电压发生器和具有内部电压发生器的LSI器件的双极MOS IC

    公开(公告)号：US5153452A

    公开(公告)日：1992-10-06

    申请号：US401849

    申请日：1989-08-30

    申请人： Masahiro Iwamura ,  Shigeya Tanaka ,  Tatsumi Yamauchi ,  Ikuro Masuda ,  Tetsuo Nakano

    发明人： Masahiro Iwamura ,  Shigeya Tanaka ,  Tatsumi Yamauchi ,  Ikuro Masuda ,  Tetsuo Nakano

    IPC分类号： H01L27/04 ,  G05F1/46 ,  G11C5/14 ,  G11C11/401 ,  G11C11/407 ,  G11C11/56 ,  H01L21/822 ,  H01L27/06

    CPC分类号： G11C11/565 ,  G05F1/465 ,  G11C5/147 ,  G11C16/30

    摘要： There are provided a bipolar-MOS IC device smaller than half-micron scale, and a combination of such IC device and external circuits. The IC device has an internal voltage generating circuit for generating an internal power source by using an external power source, the voltage of the internal power source being lower than that of the external power source. The internal voltage generating circuit includes an NPN transistor formed in an N-type region or N-type island within a P-type semiconductor substrate of the IC device, and a PMOS transistor formed in the N-type island. The collector of the NPN transistor and the source of the PMOS transistor are used as external power source terminals. The drain of the PMOS transistor is connected to the base of the NPN transistor. The gate is used as a control signal terminal. The emitter of the NPN transistor is used as an internal power source output terminal. A current path from the external power source input terminal and the internal power source output terminal is accordingly formed within the N-type island isolated from the P-type substrate.

    摘要翻译： 提供了小于半微米级的双极MOS集成电路，以及这些IC器件和外部电路的组合。 IC器件具有内部电压产生电路，用于通过使用外部电源产生内部电源，内部电源的电压低于外部电源的电压。 内部电压产生电路包括形成在IC器件的P型半导体衬底内的N型区域或N型岛中的NPN晶体管和形成在N型岛中的PMOS晶体管。 NPN晶体管的集电极和PMOS晶体管的源极用作外部电源端子。 PMOS晶体管的漏极连接到NPN晶体管的基极。 门用作控制信号端子。 NPN晶体管的发射极用作内部电源输出端子。 因此，在与P型基板隔离的N型岛中形成从外部电源输入端子和内部电源输出端子的电流路径。

    Microprocessor with improved internal transmission
    2.
    发明授权
    Microprocessor with improved internal transmission 失效
    微处理器具有改进的内部传输

    公开(公告)号：US5339448A

    公开(公告)日：1994-08-16

    申请号：US015296

    申请日：1993-01-22

    申请人： Shigeya Tanaka ,  Masahiro Iwamura ,  Tatsumi Yamauchi ,  Tatsuo Nojiri ,  Hisashi Tada ,  Tetsuo Nakano

    发明人： Shigeya Tanaka ,  Masahiro Iwamura ,  Tatsumi Yamauchi ,  Tatsuo Nojiri ,  Hisashi Tada ,  Tetsuo Nakano

    IPC分类号： G06F7/00 ,  G06F13/16 ,  G06F13/36 ,  G06F13/40 ,  G06F15/78 ,  G06F13/38

    CPC分类号： G06F13/1684 ,  G06F13/4027 ,  G06F13/4072

    摘要： A microprocessor according to the present invention comprises a sub-read bus, to which output terminals of registers of a register file of the microprocessor are coupled. The sub-read bus is in turn coupled to a main read bus of the microprocessor through a bus output circuit. Upon occurrence of a read access to any of the registers, the bus output circuit couples the sub-read bus with the main read bus, whereby data read out from the registers to the sub-read bus are transmitted to the main read bus, and under no existence of the read access, the bus output circuit interrupts the data transmission from the sub-read bus to the main read bus. With this, a load capacitance of the read bus is reduced. As a result, a time for making access to the read bus is much improved.

    摘要翻译： 根据本发明的微处理器包括子读总线，微处理器的寄存器文件的寄存器的输出端耦合到该子读总线。 子读取总线又通过总线输出电路耦合到微处理器的主读取总线。 在发生对任何寄存器的读取访问时，总线输出电路将子读总线与主读总线耦合，由此从寄存器读出到子读总线的数据被发送到主读总线， 在不存在读访问的情况下，总线输出电路中断从子读总线到主读总线的数据传输。 因此，读总线的负载电容减小。 结果，访问读总线的时间大大改善。

    Inverting logic buffer BICMOS switching circuit using an enabling switch for three-state operation with reduced dissipation
    3.
    发明授权
    Inverting logic buffer BICMOS switching circuit using an enabling switch for three-state operation with reduced dissipation 失效
    反相逻辑缓冲器BICMOS开关电路使用启用开关进行三态操作，减少耗散

    公开(公告)号：US4678943A

    公开(公告)日：1987-07-07

    申请号：US704209

    申请日：1985-02-22

    申请人： Akira Uragami ,  Yukio Suzuki ,  Shinji Kadono ,  Masahiro Iwamura ,  Ikuro Masuda ,  Tatsumi Yamauchi

    发明人： Akira Uragami ,  Yukio Suzuki ,  Shinji Kadono ,  Masahiro Iwamura ,  Ikuro Masuda ,  Tatsumi Yamauchi

    IPC分类号： H03K19/0175 ,  H03K17/04 ,  H03K17/60 ,  H03K19/0944

    CPC分类号： H03K19/09448

    摘要： A switching circuit comprises a pre-stage circuit coupled to receive an input signal and an output stage, wherein an output signal having a phase opposite to that of a signal of an input terminal IN can be obtained from an output terminal OUT of the output stage. The pre-stage circuit includes a p-channel MOSFET M1 and an n-channel MOSFET M2 that receive input signals at their gates. The output stage includes two NPN transistors Q1 and Q2 that are connected in series. The drain output of the p-channel MOSFET M1 is applied to the base of one of the transistors of the output stage, and the source output of the n-channel MOSFET M2 is applied to the base of the other of the transistors of the output stage. A third MOSFET M3 is coupled between a power supply and the p-channel MOSFET M1 and the n-channel MOSFET M2. When the MOSFET M3 is rendered non-conductive by a control signal EN, both MOSFETs M1 and M2 and both NPN transistors Q1 and Q2 become non-conductive irrespective of the signal of the input terminal IN. Under this condition, the output terminal OUT is in a floating state. Thus, the switching circuit is a tri-state circuit.

    摘要翻译： 开关电路包括耦合以接收输入信号的预级电路和输出级，其中可以从输出级的输出端OUT获得具有与输入端IN的信号相反的相位的输出信号 。 该前级电路包括在其栅极接收输入信号的p沟道MOSFET M1和n沟道MOSFET M2。 输出级包括串联连接的两个NPN晶体管Q1和Q2。 p沟道MOSFET M1的漏极输出被施加到输出级的一个晶体管的基极，并且n沟道MOSFET M2的源极输出被施加到输出的晶体管的另一个的基极 阶段。 第三个MOSFET M3耦合在电源和p沟道MOSFET M1和n沟道MOSFET M2之间。 当通过控制信号EN使MOSFET M3不导通时，无论输入端子IN的信号如何，MOSFET M1和M2以及两个NPN晶体管Q1和Q2都不导通。 在这种情况下，输出端子OUT处于浮置状态。 因此，开关电路是三态电路。

    Pipelined semiconductor devices suitable for ultra large scale integration
    4.
    发明授权
    Pipelined semiconductor devices suitable for ultra large scale integration 失效
    适用于超大规模集成的流水线半导体器件

    公开(公告)号：US06467004B1

    公开(公告)日：2002-10-15

    申请号：US09477448

    申请日：2000-01-04

    申请人： Masahiro Iwamura ,  Shigeya Tanaka ,  Takashi Hotta ,  Tatsumi Yamauchi ,  Kazutaka Mori

    发明人： Masahiro Iwamura ,  Shigeya Tanaka ,  Takashi Hotta ,  Tatsumi Yamauchi ,  Kazutaka Mori

    IPC分类号： G06F938

    CPC分类号： G06F9/3875 ,  G06F9/3869

    摘要： A high speed, high performance pipelined semiconductor device is provided, such as a pipelined data processing device and memory device. In the pipeline operation, a functional circuit unit and a transmission unit are separately controlled at each pipeline stage cycle. A transmission unit between two functional circuit units is divided into N transmission units while considering a cycle time, and each divided transmission unit is assigned one pipeline stage cycle.

    摘要翻译： 提供了一种高速，高性能流水线半导体器件，例如流水线数据处理设备和存储器件。 在流水线操作中，功能电路单元和传输单元在每个流水线级周期被单独控制。 两个功能电路单元之间的传输单元在考虑周期时间的同时被分成N个传输单元，并且每个划分的传输单元被分配一个流水线级周期。

    Semiconductor integrated circuit having logi gates
    8.
    发明授权
    Semiconductor integrated circuit having logi gates 失效
    具有逻辑门的半导体集成电路

    公开(公告)号：US5675548A

    公开(公告)日：1997-10-07

    申请号：US608605

    申请日：1996-02-29

    申请人： Yuji Yokoyama ,  Takashi Akioka ,  Masahiro Iwamura ,  Atsushi Hiraishi ,  Yutaka Kobayashi ,  Tatsumi Yamauchi ,  Shigeru Takahashi ,  Nobuyuki Gotou ,  Akira Ide

    发明人： Yuji Yokoyama ,  Takashi Akioka ,  Masahiro Iwamura ,  Atsushi Hiraishi ,  Yutaka Kobayashi ,  Tatsumi Yamauchi ,  Shigeru Takahashi ,  Nobuyuki Gotou ,  Akira Ide

    IPC分类号： G11C7/10 ,  G11C8/10 ,  H03K19/0948 ,  G11C8/00

    CPC分类号： H03K19/0948 ,  G11C7/1051 ,  G11C7/1078 ,  G11C8/10

    摘要： An arrangement which is particularly effective for decoders in semiconductor memory circuits which use, for example, common NMOS to receive one input for a plurality of logic decoder gates is provided includes a plurality of logic gates each having a first input terminal for respectively receiving first input signals and each being coupled to a common node. In one embodiment, first and second switching elements are also coupled to the common node. The first and second switching elements are both coupled to a second input terminal for receiving a second input signal which is common to the plurality of logic gates, and both operate complementary to one another in response to the second input signal. An improved read/write arrangement is also provided for such semiconductor memory circuit which includes circuitry to prevent connection of a common read line to the data lines during the writing operation. This enhances the writing speed by removing the load of the common read line during writing.

    摘要翻译： 提供了对于使用例如公共NMOS来接收多个逻辑解码器门的一个输入的半导体存储器电路中的解码器特别有效的装置，其包括多个逻辑门，每个逻辑门具有用于分别接收第一输入的第一输入端 信号，并且每个都耦合到公共节点。 在一个实施例中，第一和第二开关元件也耦合到公共节点。 第一和第二开关元件都耦合到第二输入端子，用于接收多个逻辑门公共的第二输入信号，并且它们都响应于第二输入信号互相互补。 还提供了一种用于这种半导体存储器电路的改进的读/写布置，该电路包括用于在写入操作期间公共读取线与数据线的连接的电路。 这通过在写入期间去除公共读取线的负载来增强写入速度。