公开(公告)号：US20050253174A1

公开(公告)日：2005-11-17

申请号：US11116357

申请日：2005-04-28

申请人： Masahiro Sakuragi ,  Masahiko Sonoda

发明人： Masahiro Sakuragi ,  Masahiko Sonoda

IPC分类号： H01L27/04 ,  H01L21/822 ,  H01L27/02 ,  H01L27/06 ,  H01L29/06 ,  H01L29/10 ,  H01L29/76 ,  H01L29/78

CPC分类号： H01L29/1087 ,  H01L27/0266 ,  H01L29/0696 ,  H01L29/1083 ,  H01L29/78

摘要： A MOS transistor comprises: a first conduction type region; a second conduction type drain region formed on the outermost layer portion of the first conduction type region; a second conduction type source region formed on the outermost layer portion of the first conduction type region with a channel region provided between the second conduction type drain region and the second conduction type source region; agate electrode formed on the channel region; a second conduction type base region formed inside of the second conduction type drain region in plan elevation; a plurality of first conduction type emitter regions formed in the second conduction type base region on the outermost layer portion thereof at spatial intervals in a predetermined direction; and a drain contact connected to, as lying astride, adjacent two first conduction type emitter regions and that portion of the second conduction type drain region between these adjacent two first conduction type emitter regions.

摘要翻译： MOS晶体管包括：第一导电类型区域; 形成在第一导电类型区域的最外层部分上的第二导电型漏极区域; 第二导电型源极区，形成在第一导电型区域的最外层部分上，沟道区域设置在第二导电型漏极区域和第二导电型源极区域之间; 在沟道区上形成玛瑙电极; 在平面图中形成在第二导电型漏极区域内的第二导电型基极区域; 多个第一导电型发射极区域，其在最外层部分的第二导电型基极区域中沿预定方向以空间间隔形成; 以及漏极接触件，其跨过两个相邻的两个第一导电类型发射极区域和该相邻的两个第一导电型发射极区域之间的第二导电类型漏极区域的一部分。

公开(公告)号：US07521747B2

公开(公告)日：2009-04-21

申请号：US11116357

申请日：2005-04-28

申请人： Masahiro Sakuragi ,  Masahiko Sonoda

发明人： Masahiro Sakuragi ,  Masahiko Sonoda

IPC分类号： H01L27/108 ,  H01L29/76 ,  H01L29/94 ,  H01L31/119

CPC分类号： H01L29/1087 ,  H01L27/0266 ,  H01L29/0696 ,  H01L29/1083 ,  H01L29/78

摘要： AMOS transistor comprises: a first conduction type region; a second conduction type drain region formed on the outermost layer portion of the first conduction type region; a second conduction type source region formed on the outermost layer portion of the first conduction type region with a channel region provided between the second conduction type drain region and the second conduction type source region; agate electrode formed on the channel region; a second conduction type base region formed inside of the second conduction type drain region in plan elevation; a plurality of first conduction type emitter regions formed in the second conduction type base region on the outermost layer portion thereof at spatial intervals in a predetermined direction; and a drain contact connected to, as lying astride, adjacent two first conduction type emitter regions and that portion of the second conduction type drain region between these adjacent two first conduction type emitter regions.

摘要翻译： AMOS晶体管包括：第一导电类型区域; 形成在第一导电类型区域的最外层部分上的第二导电型漏极区域; 第二导电型源极区，形成在第一导电型区域的最外层部分上，沟道区域设置在第二导电型漏极区域和第二导电型源极区域之间; 形成在沟道区上的玛瑙电极; 在平面图中形成在第二导电型漏极区域内的第二导电型基极区域; 多个第一导电型发射极区域，其在最外层部分的第二导电型基极区域中沿预定方向以空间间隔形成; 以及漏极接触件，其跨过两个相邻的两个第一导电类型发射极区域和该相邻的两个第一导电型发射极区域之间的第二导电类型漏极区域的一部分。

公开(公告)号：US20130062713A1

公开(公告)日：2013-03-14

申请号：US13699614

申请日：2011-05-25

申请人： Masahiro Sakuragi ,  Toma Fujita ,  Mizuho Okada

发明人： Masahiro Sakuragi ,  Toma Fujita ,  Mizuho Okada

IPC分类号： H01L29/84 ,  H01L21/306

CPC分类号： G01L9/0042 ,  B81B2201/0264 ,  B81B2203/0127 ,  B81C1/00158 ,  B81C2201/014 ,  G01L9/0045 ,  G01L9/0054 ,  G01L9/0073 ,  H01L21/76264 ,  H01L21/76283

摘要： [Subject] To provide a pressure sensor capable of implementing cost reduction and miniaturization.[Solving Means] A pressure sensor 1 includes a silicon substrate 2 provided therein with a reference pressure chamber 8, a diaphragm 10, consisting of part of the silicon substrate 2, formed on a surface layer portion of the silicon substrate 2 to partition a reference pressure chamber 8, and an etching stop layer 9 formed on a lower surface of the diaphragm 10 facing the reference pressure chamber 8. A through-hole 11 communicating with the reference pressure chamber 8 is formed on the diaphragm 10, and a filler 13 is arranged in the through-hole 11.

摘要翻译： 提供能够实现成本降低和小型化的压力传感器。 解决方法压力传感器1包括设置有基准压力室8的硅基板2，由硅基板2的一部分构成的振动板10，其形成在硅基板2的表层部分上，以分隔基准 压力室8和形成在隔膜10的与基准压力室8相对的下表面上的蚀刻停止层9.在隔膜10上形成有与基准压力室8连通的通孔11，填料13 布置在通孔11中。

公开(公告)号：US06917080B2

公开(公告)日：2005-07-12

申请号：US10397648

申请日：2003-03-26

申请人： Masahiro Sakuragi

发明人： Masahiro Sakuragi

IPC分类号： H01L21/331 ,  H01L21/8222 ,  H01L21/8248 ,  H01L21/8249 ,  H01L27/06 ,  H01L29/732 ,  H01L23/62 ,  H01L29/76

CPC分类号： H01L29/7322 ,  H01L27/0623

摘要： A bipolar transistor is provided, which is low in collector-to-emitter saturation voltage, small in size and to be manufactured by a reduced number of processes, and a semiconductor device formed with such a bipolar transistor and a MOS transistor on a same substrate. A high concentration region for reducing the collector-to-emitter saturation voltage VCE(sat) is formed in a manner surrounding a base region of an NPN transistor. This high concentration region is not necessarily formed in such a depth as reaching a buried layer, and can be reduced in the spread in a lateral direction. Because a high concentration region can be formed in a same process as upon forming source and drain regions for an NMOS transistor to be formed together with an NPN transistor on a same silicon substrate, it is possible to omit a diffusion process exclusive for forming a high concentration region and hence to manufacture a semiconductor device through a reduced number of processes.

公开(公告)号：US20110175637A1

公开(公告)日：2011-07-21

申请号：US12998228

申请日：2009-09-29

申请人： Goro Nakatani ,  Masahiro Sakuragi ,  Koichi Niino

发明人： Goro Nakatani ,  Masahiro Sakuragi ,  Koichi Niino

IPC分类号： G01R31/00 ,  H05K3/00 ,  H01L21/02 ,  H05K13/04

CPC分类号： G01R1/07307 ,  G01R1/07342 ,  G01R3/00 ,  G01R31/26 ,  H05K3/4084 ,  H05K2203/0195 ,  Y10T29/41 ,  Y10T29/49002 ,  Y10T29/49147 ,  Y10T29/49149 ,  Y10T29/49151 ,  Y10T29/49155 ,  Y10T29/49165

摘要： Provided is a method for manufacturing a probe card which inspects electrical characteristics of a plurality of semiconductor devices in batch. The method includes: a step of forming a plurality of probes, which are to be brought into contact with external terminals of the semiconductor devices, on one side of a board which forms the base body of the probe card; a step of forming on the board, by photolithography and etching, a plurality of through-holes which reach the probes from the other side of the board; a step of forming, in the through-holes, through electrodes to be conductively connected with the probes, respectively; and a step of forming wiring, which is conductively connected with the through electrodes, on the other side of the board.

摘要翻译： 提供一种用于制造分批检查多个半导体器件的电特性的探针卡的方法。 该方法包括：在形成探针卡的基体的基板的一侧上形成与半导体器件的外部端子接触的多个探针的步骤; 通过光刻和蚀刻在板上形成从板的另一侧到达探针的多个通孔的步骤; 在通孔中分别形成与探针导电连接的电极的步骤; 以及在所述板的另一侧上形成与所述贯通电极导电连接的布线的步骤。

公开(公告)号：US20050156249A1

公开(公告)日：2005-07-21

申请号：US11079778

申请日：2005-03-14

申请人： Masahiro Sakuragi

发明人： Masahiro Sakuragi

IPC分类号： H01L21/331 ,  H01L21/8222 ,  H01L21/8248 ,  H01L21/8249 ,  H01L27/06 ,  H01L29/732 ,  H01L23/62

CPC分类号： H01L29/7322 ,  H01L27/0623

摘要： A bipolar transistor is provided, which is low in collector-to-emitter saturation voltage, small in size and to be manufactured by a reduced number of processes, and a semiconductor device formed with such a bipolar transistor and a MOS transistor on a same substrate. A high concentration region for reducing the collector-to-emitter saturation voltage VCE(sat) is formed in a manner surrounding a base region of an NPN transistor. This high concentration region is not necessarily formed in such a depth as reaching a buried layer, and can be reduced in the spread in a lateral direction. Because a high concentration region can be formed in a same process as upon forming source and drain regions for an NMOS transistor to be formed together with an NPN transistor on a same silicon substrate, it is possible to omit a diffusion process exclusive for forming a high concentration region and hence to manufacture a semiconductor device through a reduced number of processes.

摘要翻译： 提供了一种双极晶体管，其集电极至发射极饱和电压低，尺寸小，并且由减少的工艺数量制造，并且在同一衬底上形成有这种双极晶体管和MOS晶体管的半导体器件 。 以围绕NPN晶体管的基极区域的方式形成用于降低集电极到发射极饱和电压VCE（sat）的高浓度区域。 该高浓度区域不一定形成为达到掩埋层的深度，并且可以在横向方向上扩展。 因为可以在与在同一硅衬底上与NPN晶体管一起形成的NMOS晶体管的源极和漏极区域形成相同的工艺中形成高浓度区域，所以可以省略用于形成高的浓度的扩散处理 从而通过减少数量的工艺制造半导体器件。

公开(公告)号：US07323750B2

公开(公告)日：2008-01-29

申请号：US11079778

申请日：2005-03-14

申请人： Masahiro Sakuragi

发明人： Masahiro Sakuragi

IPC分类号： H01L29/76

CPC分类号： H01L29/7322 ,  H01L27/0623

摘要： A bipolar transistor is provided, which is low in collector-to-emitter saturation voltage, small in size and to be manufactured by a reduced number of processes, and a semiconductor device formed with such a bipolar transistor and a MOS transistor on a same substrate. A high concentration region for reducing the collector-to-emitter saturation voltage VCE(sat) is formed in a manner surrounding a base region of an NPN transistor. This high concentration region is not necessarily formed in such a depth as reaching a buried layer, and can be reduced in the spread in a lateral direction. Because a high concentration region can be formed in a same process as upon forming source and drain regions for an NMOS transistor to be formed together with an NPN transistor on a same silicon substrate, it is possible to omit a diffusion process exclusive for forming a high concentration region and hence to manufacture a semiconductor device through a reduced number of processes.

摘要翻译： 提供了一种双极晶体管，其集电极至发射极饱和电压低，尺寸小，并且由减少的工艺数量制造，并且在同一衬底上形成有这种双极晶体管和MOS晶体管的半导体器件 。 以围绕NPN晶体管的基极区域的方式形成用于降低集电极到发射极饱和电压VCE（sat）的高浓度区域。 该高浓度区域不一定形成为达到掩埋层的深度，并且可以在横向方向上扩展。 因为可以以与形成与在同一硅衬底上的NPN晶体管一起形成的NMOS晶体管的源极和漏极区域相同的工艺形成高浓度区域，所以可以省略用于形成高 从而通过减少数量的工艺制造半导体器件。

公开(公告)号：US08970242B2

公开(公告)日：2015-03-03

申请号：US12998228

申请日：2009-09-29

申请人： Goro Nakatani ,  Masahiro Sakuragi ,  Koichi Niino

发明人： Goro Nakatani ,  Masahiro Sakuragi ,  Koichi Niino

IPC分类号： H01K3/10 ,  G01R1/073 ,  H05K3/40 ,  G01R3/00

CPC分类号： G01R1/07307 ,  G01R1/07342 ,  G01R3/00 ,  G01R31/26 ,  H05K3/4084 ,  H05K2203/0195 ,  Y10T29/41 ,  Y10T29/49002 ,  Y10T29/49147 ,  Y10T29/49149 ,  Y10T29/49151 ,  Y10T29/49155 ,  Y10T29/49165

摘要： Provided is a method for manufacturing a probe card which inspects electrical characteristics of a plurality of semiconductor devices in batch. The method includes: a step of forming a plurality of probes, which are to be brought into contact with external terminals of the semiconductor devices, on one side of a board which forms the base body of the probe card; a step of forming on the board, by photolithography and etching, a plurality of through-holes which reach the probes from the other side of the board; a step of forming, in the through-holes, through electrodes to be conductively connected with the probes, respectively; and a step of forming wiring, which is conductively connected with the through electrodes, on the other side of the board.

摘要翻译： 提供一种用于制造分批检查多个半导体器件的电特性的探针卡的方法。 该方法包括：在形成探针卡的基体的基板的一侧上形成与半导体器件的外部端子接触的多个探针的步骤; 通过光刻和蚀刻在板上形成从板的另一侧到达探针的多个通孔的步骤; 在通孔中分别形成与探针导电连接的电极的步骤; 以及在所述板的另一侧上形成与所述贯通电极导电连接的布线的步骤。

公开(公告)号：US08829630B2

公开(公告)日：2014-09-09

申请号：US13699614

申请日：2011-05-25

申请人： Masahiro Sakuragi ,  Toma Fujita ,  Mizuho Okada

发明人： Masahiro Sakuragi ,  Toma Fujita ,  Mizuho Okada

IPC分类号： H01L29/84 ,  B81C1/00 ,  H01L21/762 ,  G01L9/00

CPC分类号： G01L9/0042 ,  B81B2201/0264 ,  B81B2203/0127 ,  B81C1/00158 ,  B81C2201/014 ,  G01L9/0045 ,  G01L9/0054 ,  G01L9/0073 ,  H01L21/76264 ,  H01L21/76283

摘要： [Subject] To provide a pressure sensor capable of implementing cost reduction and miniaturization.[Solving Means] A pressure sensor 1 includes a silicon substrate 2 provided therein with a reference pressure chamber 8, a diaphragm 10, consisting of part of the silicon substrate 2, formed on a surface layer portion of the silicon substrate 2 to partition a reference pressure chamber 8, and an etching stop layer 9 formed on a lower surface of the diaphragm 10 facing the reference pressure chamber 8. A through-hole 11 communicating with the reference pressure chamber 8 is formed on the diaphragm 10, and a filler 13 is arranged in the through-hole 11.

摘要翻译： 提供能够实现成本降低和小型化的压力传感器。 解决方法压力传感器1包括设置有基准压力室8的硅基板2，由硅基板2的一部分构成的振动板10，其形成在硅基板2的表层部分上，以分隔基准 压力室8和形成在隔膜10的与基准压力室8相对的下表面上的蚀刻停止层9.在隔膜10上形成有与基准压力室8连通的通孔11，填料13 布置在通孔11中。

公开(公告)号：US08770035B2

公开(公告)日：2014-07-08

申请号：US13386712

申请日：2010-07-12

申请人： Nobuyuki Yamada ,  Masahiro Sakuragi ,  Takeshi Yoshida ,  Kei Hayashi

发明人： Nobuyuki Yamada ,  Masahiro Sakuragi ,  Takeshi Yoshida ,  Kei Hayashi

IPC分类号： G01L9/00 ,  H01L29/84

CPC分类号： G01L9/0051 ,  G01L9/0042 ,  G01L9/008 ,  G01L9/06 ,  G01L27/007 ,  Y10T29/49002

摘要： A semiconductor pressure sensor (720) includes a thin film piezoelectric element (701) which applies strain to a portion of a semiconductor substrate that corresponds to a thin region (402). The thin film piezoelectric element (701) is formed at a distance away from diffusion resistors (406, 408, 410, and 412) functioning as strain gauges and is extended to the proximity of a bonding pad (716A) connected to an upper electrode layer of the thin film piezoelectric element and a bonding pad (716F) connected to a lower electrode thereof. The diffusion resistors (406, 408, 410, and 412) constitute a bridge circuit by metal wiring (722) and diffusion wiring (724). During self-diagnosis, a prescribed voltage is applied to a thin film piezoelectric element (701). If the output difference of the bridge circuit between before and after the voltage application falls outside a prescribed range, it is determined that a breakage occurs in the semiconductor pressure sensor (720).

摘要翻译： 半导体压力传感器（720）包括薄膜压电元件（701），该薄膜压电元件对与薄区域（402）对应的半导体衬底的一部分施加应变。 薄膜压电元件（701）形成为远离用作应变计的扩散电阻器（406,408,410和412）的一定距离，并且延伸到接合焊盘（716A）附近的上电极层 的薄膜压电元件和连接到其下电极的接合焊盘（716F）。 扩散电阻器（406,408,410和412）通过金属布线（722）和扩散布线（724）构成桥接电路。 在自诊断期间，向薄膜压电元件（701）施加规定的电压。 如果电压施加之前和之后的桥接电路的输出差超出规定范围，则确定在半导体压力传感器（720）中发生断线。