公开(公告)号：US4939518A

公开(公告)日：1990-07-03

申请号：US248374

申请日：1988-09-23

申请人： Masao Hotta ,  Toshihiko Shimizu ,  Kenzi Maio ,  Yoshito Nejime

发明人： Masao Hotta ,  Toshihiko Shimizu ,  Kenzi Maio ,  Yoshito Nejime

IPC分类号： H03M1/12 ,  H03M1/20 ,  H03M1/36

CPC分类号： H03M1/206 ,  H03M1/1235 ,  H03M1/365

摘要： In a cyclic averaging analog to digital converter, reference voltages having a plurality of levels, each of which is inputted to one of a plurality of comparators in a flash type analog to digital converter, are shifted cyclically by a small voltage, and the outputs of the flash type analog to digital converter are added for every shift cycle in order to obtain an output digital signal. The outputs of a voltage dividing circuit provide the reference voltages with N levels, the levels differing cyclically by a small voltage. The N reference voltages are divided into groups, each of which consists of M elements N/M, switches are provided each of which selects one of the reference voltages one after another for an associated group N/M reference voltages are thus selected by these switches and are supplied to the comparators.

摘要翻译： 在循环平均模数转换器中，具有多个电平的参考电压，每个电平被输入到闪存类型模数转换器中的多个比较器中的一个，周期性地被小电压移位，并且输出 为每个移位周期添加闪存型模数转换器，以获得输出数字信号。 分压电路的输出为N个电平提供参考电压，该电平周期性地受到小电压的限制。 N个参考电压被分成组，每个组由M个元件N / M组成，提供开关，每个选择一个参考电压一个接一个地为相关联的组N / M参考电压由这些开关选择 并提供给比较器。

公开(公告)号：US4978957A

公开(公告)日：1990-12-18

申请号：US475799

申请日：1990-02-06

申请人： Masao Hotta ,  Toshihiko Shimizu ,  Yoshito Nejime

发明人： Masao Hotta ,  Toshihiko Shimizu ,  Yoshito Nejime

IPC分类号： H03M1/14 ,  H03M1/36

CPC分类号： H03M1/147 ,  H03M1/365

摘要： Disclosed is a parallel analog-to-digital converter in which a plurality of comparators are divided into a plurality of groups each consisting of a predetermined number of comparators, and outputs of at least these comparators belonging to the same group are added in an analog or digital fashion. Whether or not the result of addition of the outputs of the comparators exceeds a predetermined threshold level is decided in an analog or digital fashion so as to determine high-order and low-order bits of a digital output signal of the converter on the basis of the result of decision.

摘要翻译： 公开了一种并行模拟 - 数字转换器，其中多个比较器被分成多个组，每个组由预定数量的比较器组成，并且至少属于同一组的这些比较器的输出被添加到模拟或 数码时尚。 以模拟或数字的方式决定比较器的输出的相加结果是否超过预定阈值水平，以便基于以下方式确定转换器的数字输出信号的高阶和低位： 决定的结果。

公开(公告)号：US4866444A

公开(公告)日：1989-09-12

申请号：US154086

申请日：1988-02-09

申请人： Yoshito Nejime ,  Masao Hotta ,  Kenji Maio ,  Koichi Ono

发明人： Yoshito Nejime ,  Masao Hotta ,  Kenji Maio ,  Koichi Ono

IPC分类号： H03M1/36 ,  H03M1/00 ,  H03M1/12

CPC分类号： H03M1/0809 ,  H03M1/365

摘要： A flash type AD converter includes a group of comparators divided into blocks each including 2.sup.N comparators (N=1, 2, ---), each comparing an input signal with one of a plurality of reference signals, each having individually different voltage levels. One of the comparators may correspond to a level change point where the voltage level of the input signal is higher than that of the reference signal of that comparator which then generates a specific output different from those of the remaining comparators. The converter generates a binary-coded output on the basis of the specific output generated from the level change point comparator. When any one of the plural comparators belonging to one of the blocks generates the specific output, the specific output is applied as an inhibit signal to inhibit appearance of an output from a block including comparators having reference voltage signals with corresponding levels lower than those of the comparators of the block to which the comparator generating the specific output belongs.

摘要翻译： 闪光型AD转换器包括一组比较器，其被分成块，每个块包括2N个比较器（N = 1,2，...），每个比较器将输入信号与多个参考信号中的一个进行比较，每个参考信号具有单独不同的电压电平。 一个比较器可以对应于电平变化点，其中输入信号的电压电平高于该比较器的参考信号的电平，然后产生与剩余的比较器不同的特定输出。 转换器根据从电平变化点比较器产生的特定输出产生二进制编码输出。 当属于其中一个块的多个比较器中的任何一个产生特定输出时，该特定输出被施加作为禁止信号，以抑制来自包括比较器的输出的出现，该比较器具有的参考电压信号的相应电平低于 生成特定输出的比较器所属的块的比较器。

公开(公告)号：US5138203A

公开(公告)日：1992-08-11

申请号：US342328

申请日：1989-04-24

申请人： Koichi Ono ,  Masao Hotta ,  Yoshito Nejime

发明人： Koichi Ono ,  Masao Hotta ,  Yoshito Nejime

IPC分类号： H03M1/36 ,  H03K17/16 ,  H03K17/60 ,  H03K19/0175 ,  H03M1/06

CPC分类号： H03M1/06 ,  H03K17/16 ,  H03K17/603 ,  H03M1/365

摘要： An integrated circuit including a plurality of circuits having the same input impedance, arranged at regular intervals, and applied with a signal from a single signal source, is disclosed in which the input impedance is substantially capacitive, the characteristic impedance of a signal line connected to the signal source for sending the signal to the circuits is given by Z.sub.0 .sqroot.L/C, where L indicates the inductance of the signal line per one circuit, and C indicates the combined capacitance of the parasitic capacitance of the signal line per one circuit and the input capacitance of each circuit, the signal line is terminated by a circuit element having impedance equal to the characteristic impedance Z.sub.0, and the signal source has output impedance equal to the characteristic impedance Z.sub.0.

摘要翻译： 公开了一种集成电路，其包括具有相同输入阻抗的多个电路，以规则的间隔布置并且施加了来自单个信号源的信号，其中输入阻抗基本上是电容性的，信号线的特性阻抗连接到 用于将信号发送到电路的信号源由Z0 2ROOT L / C给出，其中L表示每个电路的信号线的电感，C表示每个电路的信号线的寄生电容的组合电容， 每个电路的输入电容，信号线由具有等于特性阻抗Z0的阻抗的电路元件端接，并且信号源具有等于特性阻抗Z0的输出阻抗。

公开(公告)号：US06226605B1

公开(公告)日：2001-05-01

申请号：US09132214

申请日：1998-08-11

申请人： Yoshito Nejime ,  Hiroshi Ikeda ,  Masao Hotta

发明人： Yoshito Nejime ,  Hiroshi Ikeda ,  Masao Hotta

IPC分类号： G10L1104

CPC分类号： H04R25/505 ,  G10L21/0232 ,  G10L21/0364 ,  G10L21/04 ,  H04R1/005 ,  H04R5/04 ,  H04R25/70 ,  H04R2205/041 ,  H04R2225/43

摘要： Making use of a digital acoustic signal processing apparatus arranged by employing memory device for storing a digital acoustic signal, acoustic frequency feature enhancing device for enhancing an acoustic frequency feature, and low-speed sound reproducing device for changing a speed of the stored voice to reproduce this voice as a low speed into a hearing aid and an appliance with an acoustic output, a hearing function difficulty due to an age is aided in utilization of audio output appliances such as a hearing aid, television receiver, and a telephone receiver. After the voice has been stored in the memory device, a process for enhancing the frequency characteristic in order to fit the frequency characteristic to the individual hearing characteristic and the voice reproducing environment is carried out and thereafter represented to the user. The user can repeatedly listen the voice stored in the memory device with employment of control device for controlling the voice reproducing operation. Furthermore, since a process for expanding a time scale during a sound reproducing operation is carried out, the voice can be represented at the low speed. Since the voice whose frequency characteristic has been enhanced can be represented at the low speed in order that either an individual hearing ability, or an apparatus is fitted to a using environment, hearing articulation can be improved with respect to such a hearing, the frequency resolution and the time resolution are simultaneously deteriorated.

摘要翻译： 利用通过采用用于存储数字声音信号的存储装置而布置的数字声信号处理装置，用于增强声频特征的声频特征增强装置和用于改变所存储的声音的速度以便再现的低速声音再现装置 这种声音作为低速进入助听器和具有声学输出的器具，由于年龄而引起的听力功能困难有助于使用诸如助听器，电视接收机和电话接收器的音频输出设备。 在语音已被存储在存储装置中之后，执行用于增强频率特性以便将频率特性适应于个人听觉特性和语音再现环境的过程，并且此后表示给用户。 用户可以通过使用用于控制语音再现操作的控制装置来重复监听存储在存储设备中的语音。 此外，由于执行在声音再现操作期间扩展时标的处理，所以可以以低速表示声音。 由于频率特性已被增强的声音可以以低速表示，以便将单独的听觉能力或装置安装在使用环境中，可以相对于这种听觉改善听觉发音，频率分辨率 并且时间分辨率同时恶化。

公开(公告)号：US5794201A

公开(公告)日：1998-08-11

申请号：US462268

申请日：1995-06-05

申请人： Yoshito Nejime ,  Hiroshi Ikeda ,  Masao Hotta

发明人： Yoshito Nejime ,  Hiroshi Ikeda ,  Masao Hotta

IPC分类号： G10L21/02 ,  G10L21/0232 ,  G10L21/04 ,  H04R1/00 ,  H04R5/04 ,  H04R25/00 ,  G10L3/00 ,  G10L3/02 ,  G10L9/00

CPC分类号： H04R25/505 ,  G10L21/0364 ,  G10L21/04 ,  H04R1/005 ,  H04R5/04 ,  G10L21/0232 ,  H04R2205/041 ,  H04R2225/43 ,  H04R25/70

摘要： Making use of a digital acoustic signal processing apparatus arranged by employing memory device for storing a digital acoustic signal, acoustic frequency feature enhancing device for enhancing an acoustic frequency feature, and low-speed sound reproducing device for changing a speed of the stored voice to reproduce this voice as a low speed into a hearing aid and an appliance with an acoustic output, a hearing function difficulty due to an age is aided in utilization of audio output appliances such as a hearing aid, television receiver, and a telephone receiver. After the voice has been stored in the memory device, a process for enhancing the frequency characteristic in order to fit the frequency characteristic to the individual hearing characteristic and the voice reproducing environment is carried out and thereafter represented to the user. The user can repeatedly listen the voice stored in the memory device with employment of control device for controlling the voice reproducing operation. Furthermore, since a process for expanding a time scale during a sound reproducing operation is carried out, the voice can be represented at the low speed. Since the voice whose frequency characteristic has been enhanced can be represented at the low speed in order that either an individual hearing ability, or an apparatus is fitted to a using environment, hearing articulation can be improved with respect to such a hearing, the frequency resolution and the time resolution are simultaneously deteriorated.

摘要翻译： 利用通过采用用于存储数字声音信号的存储装置而布置的数字声信号处理装置，用于增强声频特征的声频特征增强装置和用于改变所存储的声音的速度以便再现的低速声音再现装置 这种声音作为低速进入助听器和具有声学输出的器具，由于年龄而引起的听力功能困难有助于使用诸如助听器，电视接收机和电话接收器的音频输出设备。 在语音已被存储在存储装置中之后，执行用于增强频率特性以便将频率特性适应于个人听觉特性和语音再现环境的过程，并且此后表示给用户。 用户可以通过使用用于控制语音再现操作的控制装置来重复监听存储在存储设备中的语音。 此外，由于执行在声音再现操作期间扩展时标的处理，所以可以以低速表示声音。 由于频率特性已被增强的声音可以以低速表示，以便将单独的听觉能力或装置安装到使用环境中，可以相对于这种听觉改善听觉发音，频率分辨率 并且时间分辨率同时恶化。

公开(公告)号：US5113077A

公开(公告)日：1992-05-12

申请号：US588718

申请日：1990-09-27

申请人： Toshihiko Shimizu ,  Masao Hotta ,  Atsushi Moritani

发明人： Toshihiko Shimizu ,  Masao Hotta ,  Atsushi Moritani

IPC分类号： A61B6/03 ,  G01T1/17 ,  G01T1/20 ,  G01T1/29

CPC分类号： G01T1/17 ,  G01T1/2985

摘要： A radiation detection circuit integrates output currents of a plurality of X-ray CT scanner radiation detectors, which are combinations of scintillators and photodiodes, during a short period to convert them to charge information in order to collect data for reproducing a tomogram. A current amplifier is connected to the output terminal of the photo-diode, and an output current of the current amplifier is charged in an integration capacitor. In this manner, the radiation detection circuit enables reduction of the measurement period.

摘要翻译： 辐射检测电路在短时间内将作为闪烁体和光电二极管的组合的多个X射线CT扫描仪辐射检测器的输出电流进行积分，以将其转换为电荷信息，以便收集用于再现断层图像的数据。 电流放大器连接到光电二极管的输出端，并且电流放大器的输出电流在积分电容器中充电。 以这种方式，辐射检测电路能够减少测量周期。

公开(公告)号：US4875048A

公开(公告)日：1989-10-17

申请号：US237757

申请日：1988-08-29

申请人： Toshihiko Shimizu ,  Masao Hotta ,  Kenji Maio

发明人： Toshihiko Shimizu ,  Masao Hotta ,  Kenji Maio

IPC分类号： H03M1/14 ,  H03M1/00 ,  H03M1/10

CPC分类号： H03M1/10 ,  H03M1/16 ,  H03M1/361

摘要： In a two-step parallel analog to digital converter of the type in which a first flash-type A/D converter determines the upper significant bits of a digital signal output having a desired number of bits and after a quantizing error of the first flash-type A/D converter has been determined from the difference between a value obtained by reconverting the upper significant bits to an analog value and the input analog value a second flash-type A/D converter subjects the quantizing error to A/D conversion to determine a digital output of the remaining lower significant bits, a gain correcting circuit is additionally provided to automatically establish a gain of a D/A converter for reconverting the upper significant bits to an analog value on the basis of a reference voltage applied to the first flash-type A/D converter. Moreover, a reference voltage generating circuit is additionally provided to establish upper and lower reference voltages of a second flash-type A/D converter for determining lower significant bits on the basis of the step voltage of the DAC output.

摘要翻译： 在两级并行模数转换器中，其中第一闪存型A / D转换器确定具有所需位数的数字信号输出的高有效位，并且在第一闪存型A / D转换器的量化误差之后， 已经根据通过将高有效位重新转换为模拟值而获得的值与输入模拟值之间的差确定了A / D转换器，第二闪存型A / D转换器将量化误差对A / D转换进行测量，以确定 附加提供增益校正电路以自动建立D / A转换器的增益，用于根据施加到第一闪存的参考电压将高有效位重新转换为模拟值 型A / D转换器。 此外，另外提供参考电压产生电路以建立第二闪存型A / D转换器的上限和下限参考电压，用于基于DAC输出的阶跃电压来确定较低有效位。

公开(公告)号：US4752766A

公开(公告)日：1988-06-21

申请号：US15017

申请日：1987-02-17

申请人： Toshihiko Shimizu ,  Masao Hotta ,  Kenji Maio

发明人： Toshihiko Shimizu ,  Masao Hotta ,  Kenji Maio

IPC分类号： H03M1/36 ,  H03M1/00 ,  H03M1/06

CPC分类号： H03M1/361

摘要： In an analog-to-digital converter of a parallel comparison type having a plurality of comparators for comparing an analog input voltage with different reference voltages and converting a comparison result into a digital output by means of an encoder, a plurality of comparators each having a different input dynamic range are used to widen the analog input voltage range up to the power source range of positive and negative voltages.

摘要翻译： 在具有用于将模拟输入电压与不同参考电压进行比较的多个比较器并且通过编码器将比较结果转换成数字输出的并行比较类型的模拟 - 数字转换器中，每个具有 不同的输入动态范围用于将模拟输入电压范围扩大到正，负电压的电源范围。

公开(公告)号：US4916653A

公开(公告)日：1990-04-10

申请号：US235528

申请日：1988-08-24

申请人： Toshihiko Shimizu ,  Masao Hotta

发明人： Toshihiko Shimizu ,  Masao Hotta

IPC分类号： G06G7/14 ,  G06F7/50 ,  G06F7/501 ,  G06F7/503 ,  G06F7/506 ,  G06J1/00

CPC分类号： G06F7/5013

摘要： A binary digital full adder as a component element of a digital circuit receives three binary signals including two input signals and a carry-in from the lower digit. The adder comprises a four-state logic converter for adding together the three binary signals in terms of current addition to convert the sum into a four-state logic signal, and an encoder for deciding a four-state logic level to encode it into a binary sum and a carry-out.

摘要翻译： 作为数字电路的元件的二进制数字全加器接收包括两个输入信号的三个二进制信号和来自较低数字的进位输入。 加法器包括四状态逻辑转换器，用于将电流相加的三个二进制信号相加在一起，以将和转换成四态逻辑信号;以及编码器，用于确定四态逻辑电平以将其编码为二进制 总和和进行。