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公开(公告)号：US07068551B2
公开(公告)日：2006-06-27
申请号：US11046690
申请日：2005-02-01
IPC分类号： G11C7/00
CPC分类号： G11C5/063 , G11C7/02 , G11C7/1048 , G11C7/18 , G11C11/419 , H01L27/11
摘要： Parasitic capacitances formed between bit lines to which signals are to be read out of memory cells and a signal transmission line arranged above them are to be reduced. Second complementary global bit lines for transmitting data read out of memory cells MC via complementary bit lines are arranged above a memory cell array. Each second global bit line is so arranged that a triangle having as its vertexes the center of the section of one of the complementary bit lines, that of the section of the other and that of the section of the second global bit line arranged directly above these complementary bit lines be an isosceles triangle.
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公开(公告)号：US20060158918A1
公开(公告)日：2006-07-20
申请号：US11375060
申请日：2006-03-15
IPC分类号： G11C5/06
CPC分类号： G11C5/063 , G11C7/02 , G11C7/1048 , G11C7/18 , G11C11/419 , H01L27/11
摘要： Parasitic capacitances formed between bit lines to which signals are to be read out of memory cells and a signal transmission line arranged above them are to be reduced. Second complementary global bit lines for transmitting data read out of memory cells MC via complementary bit lines are arranged above a memory cell array. Each second global bit line is so arranged that a triangle having as its vertexes the center of the section of one of the complementary bit lines, that of the section of the other and that of the section of the second global bit line arranged directly above these complementary bit lines be an isosceles triangle.
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公开(公告)号：US06770941B2
公开(公告)日：2004-08-03
申请号：US10002009
申请日：2001-12-05
申请人： Masao Shinozaki , Takashi Akioka , Kinya Mitsumoto
发明人： Masao Shinozaki , Takashi Akioka , Kinya Mitsumoto
IPC分类号： H01L2976
CPC分类号： H01L27/088 , H01L21/823412 , H01L21/823456 , H01L21/823462
摘要： The invention provides a method of producing a semiconductor device conforming to plural supply voltage specifications without increasing the chip size and the production cost, while the device achieves a high-speed performance. The method includes plural processes for forming plural types of MOS transistors supplied with different power supply voltages in correspondence with external power supply voltages, which are comprised of a first process common to the plural types of MOS transistors, a second process following the first process, which is different by each of the plural types of MOS transistors, and a third process following the second process, which is common to the plural types of MOS transistors.
摘要翻译： 本发明提供一种在不增加芯片尺寸和生产成本的情况下制造符合多种电源电压规格的半导体器件的方法，同时器件实现高速性能。 该方法包括多个处理，用于形成与外部电源电压相对应地供应不同电源电压的多种类型的MOS晶体管，这些外部电源电压由多种类型的MOS晶体管共同的第一种处理，第一种处理之后的第二种处理， 这是多种类型的MOS晶体管中的每一种不同的，以及第二种处理之后的第三种处理，这对于多种类型的MOS晶体管是共同的。
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公开(公告)号：US07254068B2
公开(公告)日：2007-08-07
申请号：US11375060
申请日：2006-03-15
IPC分类号： G11C7/00
CPC分类号： G11C5/063 , G11C7/02 , G11C7/1048 , G11C7/18 , G11C11/419 , H01L27/11
摘要： Parasitic capacitances formed between bit lines to which signals are to be read out of memory cells and a signal transmission line arranged above them are to be reduced. Second complementary global bit lines for transmitting data read out of memory cells MC via complementary bit lines are arranged above a memory cell array. Each second global bit line is so arranged that a triangle having as its vertexes the center of the section of one of the complementary bit lines, that of the section of the other and that of the section of the second global bit line arranged directly above these complementary bit lines be an isosceles triangle.
摘要翻译： 为了减少在存储单元读出信号的位线和布置在其上方的信号传输线之间形成的寄生电容。 用于通过互补位线传送从存储单元MC读出的数据的第二互补全局位线布置在存储单元阵列的上方。 每个第二全局位线被布置成使得具有顶点为互补位线之一的部分的中心的三角形，另一个的另一个的部分的中心和第二全局位线的截面的中心位于这些 互补位线是一个等腰三角形。
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公开(公告)号：US20050128839A1
公开(公告)日：2005-06-16
申请号：US11046690
申请日：2005-02-01
IPC分类号： G11C11/41 , G11C7/10 , G11C7/18 , G11C11/419 , H01L21/8244 , H01L27/11 , G11C7/00
CPC分类号： G11C5/063 , G11C7/02 , G11C7/1048 , G11C7/18 , G11C11/419 , H01L27/11
摘要： Parasitic capacitances formed between bit lines to which signals are to be read out of memory cells and a signal transmission line arranged above them are to be reduced. Second complementary global bit lines for transmitting data read out of memory cells MC via complementary bit lines are arranged above a memory cell array. Each second global bit line is so arranged that a triangle having as its vertexes the center of the section of one of the complementary bit lines, that of the section of the other and that of the section of the second global bit line arranged directly above these complementary bit lines be an isosceles triangle.
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公开(公告)号：US06856559B2
公开(公告)日：2005-02-15
申请号：US10637549
申请日：2003-08-11
IPC分类号： G11C11/41 , G11C7/10 , G11C7/18 , G11C11/419 , H01L21/8244 , H01L27/11 , G11C7/00
CPC分类号： G11C5/063 , G11C7/02 , G11C7/1048 , G11C7/18 , G11C11/419 , H01L27/11
摘要： Parasitic capacitances formed between bit lines to which signals are to be read out of memory cells and a signal transmission line arranged above them are to be reduced. Second complementary global bit lines for transmitting data read out of memory cells MC via complementary bit lines are arranged above a memory cell array. Each second global bit line is so arranged that a triangle having as its vertexes the center of the section of one of the complementary bit lines, that of the section of the other and that of the section of the second global bit line arranged directly above these complementary bit lines be an isosceles triangle.
摘要翻译： 为了减少在存储单元读出信号的位线和布置在其上方的信号传输线之间形成的寄生电容。 用于通过互补位线传送从存储单元MC读出的数据的第二互补全局位线布置在存储单元阵列的上方。 每个第二全局位线被布置成使得具有顶点为互补位线之一的部分的中心的三角形，另一个的另一个的部分的中心和第二全局位线的部分的直线布置在其上方 互补位线是一个等腰三角形。
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公开(公告)号：US06625070B2
公开(公告)日：2003-09-23
申请号：US10011488
申请日：2001-12-11
IPC分类号： G11C700
CPC分类号： G11C5/063 , G11C7/02 , G11C7/1048 , G11C7/18 , G11C11/419 , H01L27/11
摘要： Parasitic capacitances formed between bit lines to which signals are to be read out of memory cells and a signal transmission line arranged above them are to be reduced. Second complementary global bit lines for transmitting data read out of memory cells MC via complementary bit lines are arranged above a memory cell array. Each second global bit line is so arranged that a triangle having as its vertexes the center of the section of one of the complementary bit lines, that of the section of the other and that of the section of the second global bit line arranged directly above these complementary bit lines be an isosceles triangle.
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8.发明授权Logic gate circuit and parallel bit test circuit for semiconductor memory devices, capable of operation at low power source levels 失效用于半导体存储器件的逻辑门电路和并行位测试电路，能够在低电源电平下工作
公开(公告)号：US5646897A
公开(公告)日：1997-07-08
申请号：US426384
申请日：1995-04-21
CPC分类号： G11C29/028 , G11C29/50 , G11C7/1051 , G11C11/41 , G11C2029/5004 , G11C29/34
摘要： A logic circuit is provided for a memory device which can be operated at a high speed with a lower voltage power source level than conventional devices. This logic circuit can be used in a multi-bit test circuit executing the wired-OR-logic operation of complementary logic signals from a plurality of pre-sense amplifiers, receiving the output of the wired-OR-logic operation by an emitter follower using a bipolar transistor, and outputting an AND signal of the complementary logic signals by a level comparing circuit. A sense amplifier is also provided for executing the wired-OR-logic operation of complementary logic signals from a plurality of pre-sense amplifiers, raising the level of the output of the wired-OR-logic operation by a level shift circuit having a semiconductor element for applying an inverse bias potential to an input signal, executing the wired-OR-operation of the shifted up output and outputs from other blocks, and receiving and amplifying the output of the wired-OR-logic operation.
摘要翻译： 提供了一种用于存储器件的逻辑电路，其可以以比传统器件更低的电压电源电平在高速下操作。 该逻辑电路可以用于执行来自多个预读取放大器的互补逻辑信号的有线或逻辑运算的多位测试电路，通过射极跟随器接收有线或逻辑运算的输出，使用 双极晶体管，并通过电平比较电路输出互补逻辑信号的“与”信号。 还提供读出放大器，用于执行来自多个预读放大器的互补逻辑信号的有线或逻辑运算，通过具有半导体的电平移位电路提高布线或逻辑运算的输出电平 元件，用于对输入信号施加反向偏置电位，执行移位上升输出的线或运算和其他块的输出，以及接收和放大有线逻辑运算的输出。
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公开(公告)号：US5761150A
公开(公告)日：1998-06-02
申请号：US651873
申请日：1996-05-21
IPC分类号： G11C11/413 , G06F12/00 , G11C7/10 , G11C8/06 , G11C11/401 , G11C11/407 , G11C11/418 , G11C8/00 , G11C7/00
CPC分类号： G11C8/06 , G11C11/418 , G11C7/1072 , G11C2207/2218
摘要： There is provided a method of controlling an internal address signal of an RAM in which a late-write method is realized on a chip. Two sets of address registers for reading and writing are provided for each address and further a middle register is provided between the two sets of address registers. The middle register is controlled by a signal formed by obtaining the AND result of a clock signal and a write enable signal and the two sets of address registers for reading and writing are controlled only by the clock signal. A selection circuit selects outputs of the two sets of address registers as an input in accordance with the write enable signal to control an internal address.
摘要翻译： 提供了一种控制RAM的内部地址信号的方法，其中在芯片上实现了后期写入方法。 为每个地址提供两组用于读取和写入的地址寄存器，并且还在两组地址寄存器之间提供中间寄存器。 中间寄存器由通过获得时钟信号和写入使能信号的AND结果而形成的信号控制，并且用于读取和写入的两组地址寄存器仅由时钟信号控制。 选择电路根据写使能信号选择两组地址寄存器的输出作为输入，以控制内部地址。
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10.发明授权High-speed semiconductor memory device and data processing system using the same 失效高速半导体存储器件和数据处理系统使用相同
公开(公告)号：US5654931A
公开(公告)日：1997-08-05
申请号：US213531
申请日：1994-03-16
申请人： Akihiro Tamba , Masahiro Iwamura , Yutaka Kobayashi , Kinya Mitsumoto , Tatsumi Yamauchi , Shuko Yamauchi , Takashi Akioka
发明人： Akihiro Tamba , Masahiro Iwamura , Yutaka Kobayashi , Kinya Mitsumoto , Tatsumi Yamauchi , Shuko Yamauchi , Takashi Akioka
CPC分类号： G11C7/22
摘要： A semiconductor integrated circuit device is divided into a plurality of blocks, which are individually equipped with signal generate units such that the signal generate units are distributed in the semiconductor integrated circuit device. The semiconductor integrated circuit device is preferably constructed to generate the pulse signal by the pulse generate units which are provided for the individual blocks, after all initial logic operations on the data and control signals have been taken. Thanks to this construction, an SRAM, for example, can have its write recovery time minimized to 0 so that it can achieve high-speed operations. Moreover, since predecoders are provided for the individual blocks, the wiring line number and area in the chip can be reduced to improve the degree of integration of the semiconductor integrated circuit device. Still moreover, signal delay and skew can be reduced in the chip so that high-speed can be achieved. Another feature is that either the input/output pads of the data into or out of the semiconductor integrated circuit device or their accompanying circuit units are distributed in the semiconductor integrated circuit device. The individual features described above can be used solely or in combination, if necessary, to achieve the above-specified objects.
摘要翻译： 半导体集成电路器件被分成多个块，它们分别配备有信号生成单元，使得信号生成单元分布在半导体集成电路器件中。 优选地，半导体集成电路器件被构造为在对数据和控制信号进行了所有初始逻辑运算之后，通过针对各个块提供的脉冲产生单元产生脉冲信号。 由于这种结构，例如，SRAM可以将其写恢复时间最小化为0，从而可以实现高速操作。 此外，由于为每个块提供预编码器，所以可以减少芯片中的布线数量和面积，以提高半导体集成电路器件的集成度。 此外，芯片中的信号延迟和偏斜可以降低，从而可以实现高速度。 另一个特征是将半导体集成电路器件的数据的输入/输出焊盘或其相应的电路单元分布在半导体集成电路器件中。 如果需要，可以单独地或组合地使用上述各个特征来实现上述目的。
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