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    SEMICONDUCTOR DEVICE MANUFACTURING METHOD
    2.
    发明申请
    SEMICONDUCTOR DEVICE MANUFACTURING METHOD 有权
    半导体器件制造方法

    公开(公告)号：US20120282743A1

    公开(公告)日：2012-11-08

    申请号：US13487295

    申请日：2012-06-04

    申请人： Masumi SAITOH ,  Toshinori Numata ,  Yukio Nakabayashi

    发明人： Masumi SAITOH ,  Toshinori Numata ,  Yukio Nakabayashi

    IPC分类号： H01L21/336

    CPC分类号： H01L27/0207 ,  H01L21/266 ,  H01L21/823437 ,  H01L21/823462 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/66628 ,  H01L29/785

    摘要： In a semiconductor device manufacturing method, a first semiconductor region which includes a narrow portion and a wide portion is formed in an upper portion of a semiconductor substrate, a gate insulating film is formed on at least side surfaces of the narrow portion, a gate electrode is formed on the gate insulating film, a mask pattern that covers the wide portion is formed, ion implantation of an impurity is performed with the mask pattern as a mask to form an extension impurity region in the narrow portion, the mask pattern is removed, a heat treatment is performed to activate the impurity, a gate sidewall is formed on a side surface of the gate electrode, epitaxial growth of a semiconductor film is performed on the narrow portion and the wide portion after the formation of the gate sidewall, and source-drain regions is formed on both sides of the gate electrode.

    摘要翻译： 在半导体器件制造方法中，在半导体衬底的上部形成包括窄部分和宽部分的第一半导体区域，在所述窄部分的至少侧表面上形成栅极绝缘膜，栅电极 形成在栅极绝缘膜上，形成覆盖该宽部的掩模图形，利用掩模图案作为掩模进行杂质的离子注入，以在狭窄部分形成延伸杂质区，除去掩模图案， 执行热处理以激活杂质，在栅电极的侧表面上形成栅极侧壁，在形成栅极侧壁的狭窄部分和宽部分之后进行半导体膜的外延生长，源 在栅电极的两侧形成有引线区域。

    SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
    3.
    发明申请
    SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME 审中-公开
    半导体器件及其制造方法

    公开(公告)号：US20120146053A1

    公开(公告)日：2012-06-14

    申请号：US13237697

    申请日：2011-09-20

    申请人： Masumi SAITOH ,  Toshinori Numata ,  Yukio Nakabayashi ,  Kensuke Ota

    发明人： Masumi SAITOH ,  Toshinori Numata ,  Yukio Nakabayashi ,  Kensuke Ota

    IPC分类号： H01L29/161 ,  H01L21/336 ,  H01L29/78

    CPC分类号： H01L29/785 ,  H01L29/66795 ,  H01L29/7843

    摘要： A semiconductor device according to an embodiment includes a semiconductor substrate, a gate insulating film formed on the semiconductor substrate, a gate electrode formed on the gate insulating film, first gate sidewalls formed on both sides of the gate electrode, and a source/drain semiconductor layer formed on the semiconductor substrate to sandwich the first gate sidewalls with the gate electrode. Further, second gate sidewalls are provided on the first gate sidewalls and the source/drain semiconductor layer at both sides of the gate electrode, wherein the boundary of each of the second gate sidewalls with each of the first gate sidewalls is terminated at the side surface of the gate electrode, and each of the second gate sidewalls has a smaller Young's modulus and a lower dielectric constant than each of the first gate sidewalls.

    摘要翻译： 根据实施例的半导体器件包括半导体衬底，形成在半导体衬底上的栅极绝缘膜，形成在栅极绝缘膜上的栅电极，形成在栅电极两侧的第一栅极侧壁和源极/漏极半导体 层，形成在半导体衬底上，以与栅电极夹住第一栅极侧壁。 此外，第二栅极侧壁设置在栅电极两侧的第一栅极侧壁和源极/漏极半导体层上，其中每个第二栅极侧壁与每个第一栅极侧壁的边界在侧表面终止 并且每个第二栅极侧壁具有比每个第一栅极侧壁更小的杨氏模量和更低的介电常数。

    Semiconductor device manufacturing method
    4.
    发明授权
    Semiconductor device manufacturing method 有权
    半导体器件制造方法

    公开(公告)号：US08492219B2

    公开(公告)日：2013-07-23

    申请号：US13487295

    申请日：2012-06-04

    申请人： Masumi Saitoh ,  Toshinori Numata ,  Yukio Nakabayashi

    发明人： Masumi Saitoh ,  Toshinori Numata ,  Yukio Nakabayashi

    IPC分类号： H01L21/8234 ,  H01L21/337 ,  H01L21/8232 ,  H01L21/336 ,  H01L21/00

    CPC分类号： H01L27/0207 ,  H01L21/266 ,  H01L21/823437 ,  H01L21/823462 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/66628 ,  H01L29/785

    摘要： In a semiconductor device manufacturing method, a first semiconductor region which includes a narrow portion and a wide portion is formed in an upper portion of a semiconductor substrate, a gate insulating film is formed on at least side surfaces of the narrow portion, a gate electrode is formed on the gate insulating film, a mask pattern that covers the wide portion is formed, ion implantation of an impurity is performed with the mask pattern as a mask to form an extension impurity region in the narrow portion, the mask pattern is removed, a heat treatment is performed to activate the impurity, a gate sidewall is formed on a side surface of the gate electrode, epitaxial growth of a semiconductor film is performed on the narrow portion and the wide portion after the formation of the gate sidewall, and source-drain regions is formed on both sides of the gate electrode.

    摘要翻译： 在半导体器件制造方法中，在半导体衬底的上部形成包括窄部分和宽部分的第一半导体区域，在所述窄部分的至少侧表面上形成栅极绝缘膜，栅电极 形成在栅极绝缘膜上，形成覆盖该宽部的掩模图形，利用掩模图案作为掩模进行杂质的离子注入，以在狭窄部分形成延伸杂质区，除去掩模图案， 执行热处理以激活杂质，在栅电极的侧表面上形成栅极侧壁，在形成栅极侧壁的狭窄部分和宽部分之后进行半导体膜的外延生长，源 在栅电极的两侧形成有引线区域。

    SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME
    7.
    发明申请
    SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME 有权
    半导体器件及其制造方法

    公开(公告)号：US20120235152A1

    公开(公告)日：2012-09-20

    申请号：US13236199

    申请日：2011-09-19

    申请人： Kensuke OTA ,  Masumi Saitoh ,  Toshinori Numata

    发明人： Kensuke OTA ,  Masumi Saitoh ,  Toshinori Numata

    IPC分类号： H01L29/78 ,  H01L21/336

    CPC分类号： H01L29/0673 ,  H01L21/26506 ,  H01L21/26586 ,  H01L29/42392 ,  H01L29/66742 ,  H01L29/66803 ,  H01L29/785 ,  H01L29/78696

    摘要： A semiconductor device according to an embodiment includes: a polycrystalline semiconductor layer formed on an insulating film, the polycrystalline semiconductor layer including a first region and second and third regions each having a greater width than the first region, one of the second and third regions being connected to the first region; a gate insulating film formed at least on side faces of the first region of the polycrystalline semiconductor layer; a gate electrode formed on the gate insulating film; and gate sidewalls made of an insulating material, the gate sidewalls being formed on side faces of the gate electrode on sides of the second and third regions. Content of an impurity per unit volume in the first region is larger than content of the impurity per unit volume in the second and third regions.

    摘要翻译： 根据实施例的半导体器件包括：形成在绝缘膜上的多晶半导体层，所述多晶半导体层包括第一区域和第二和第三区域，所述第二区域和第三区域各自具有比所述第一区域更大的宽度，所述第二和第三区域中的一个是 连接到第一区域; 形成在所述多晶半导体层的所述第一区域的至少一侧面上的栅极绝缘膜; 形成在栅极绝缘膜上的栅电极; 以及由绝缘材料制成的栅极侧壁，所述栅极侧壁形成在所述第二和第三区域侧面上的所述栅电极的侧面上。 第一区域中每单位体积杂质的含量大于第二和第三区域中每单位体积杂质的含量。

    Nanowire channel field effect device and method for manufacturing the same
    8.
    发明授权
    Nanowire channel field effect device and method for manufacturing the same 有权
    纳米线通道场效应装置及其制造方法

    公开(公告)号：US08999801B2

    公开(公告)日：2015-04-07

    申请号：US13236199

    申请日：2011-09-19

    申请人： Kensuke Ota ,  Masumi Saitoh ,  Toshinori Numata

    发明人： Kensuke Ota ,  Masumi Saitoh ,  Toshinori Numata

    IPC分类号： H01L21/336 ,  H01L29/10 ,  H01L29/06 ,  H01L29/66 ,  H01L29/78 ,  H01L21/265

    CPC分类号： H01L29/0673 ,  H01L21/26506 ,  H01L21/26586 ,  H01L29/42392 ,  H01L29/66742 ,  H01L29/66803 ,  H01L29/785 ,  H01L29/78696

    摘要： A semiconductor device according to an embodiment includes: a polycrystalline semiconductor layer formed on an insulating film, the polycrystalline semiconductor layer including a first region and second and third regions each having a greater width than the first region, one of the second and third regions being connected to the first region; a gate insulating film formed at least on side faces of the first region of the polycrystalline semiconductor layer; a gate electrode formed on the gate insulating film; and gate sidewalls made of an insulating material, the gate sidewalls being formed on side faces of the gate electrode on sides of the second and third regions. Content of an impurity per unit volume in the first region is larger than content of the impurity per unit volume in the second and third regions.

    摘要翻译： 根据实施例的半导体器件包括：形成在绝缘膜上的多晶半导体层，所述多晶半导体层包括第一区域和第二和第三区域，所述第二区域和第三区域各自具有比所述第一区域更大的宽度，所述第二和第三区域中的一个是 连接到第一区域; 形成在所述多晶半导体层的所述第一区域的至少一侧面上的栅极绝缘膜; 形成在栅极绝缘膜上的栅电极; 以及由绝缘材料制成的栅极侧壁，所述栅极侧壁形成在所述第二和第三区域侧面上的所述栅电极的侧面上。 第一区域中每单位体积杂质的含量大于第二和第三区域中每单位体积杂质的含量。

    Semiconductor device and method of manufacturing the same
    10.
    发明授权
    Semiconductor device and method of manufacturing the same 有权
    半导体装置及其制造方法

    公开(公告)号：US08518769B2

    公开(公告)日：2013-08-27

    申请号：US13415592

    申请日：2012-03-08

    申请人： Kensuke Ota ,  Toshinori Numata ,  Masumi Saitoh ,  Chika Tanaka

    发明人： Kensuke Ota ,  Toshinori Numata ,  Masumi Saitoh ,  Chika Tanaka

    IPC分类号： H01L29/78 ,  H01L21/336

    CPC分类号： H01L29/786 ,  H01L29/00 ,  H01L29/785 ,  H01L29/78696

    摘要： A semiconductor device of an embodiment includes: an insulating film including: a first region extending in a first direction; second and third regions arranged at a distance from each other; and fourth and fifth regions each having a concave shape, the fourth and fifth regions each having a smaller film thickness than a film thickness of each of the first through third regions; a semiconductor layer formed in a direction from the fourth region toward the fifth region, the semiconductor layer having a smaller width than a width of each of source and drain regions, the semiconductor layer being connected to the source and drain regions; a gate electrode placed on the opposite side of a gate insulating film from the semiconductor layer on the first region; and a gate sidewall formed on a side face of the gate electrode.

    摘要翻译： 实施例的半导体器件包括：绝缘膜，包括：沿第一方向延伸的第一区域; 第二和第三区域彼此相隔一定距离; 第四和第五区域各自具有凹形形状，第四和第五区域各自具有比每个第一至第三区域的膜厚度更薄的膜厚度; 在从第四区域朝向第五区域的方向上形成的半导体层，所述半导体层的宽度小于源极和漏极区域的宽度，所述半导体层连接到所述源极和漏极区域; 栅极电极，位于栅极绝缘膜的与第一区域上的半导体层相反的一侧; 以及形成在栅电极的侧面上的栅极侧壁。