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公开(公告)号：US20060262620A1
公开(公告)日：2006-11-23
申请号：US11493060
申请日：2006-07-26
IPC分类号： G11C7/00
CPC分类号： G11C7/106 , G11C7/06 , G11C7/062 , G11C7/1051 , G11C7/1069 , G11C11/56 , G11C11/5642 , G11C2211/5642
摘要： In accordance with one embodiment, a serial sensing scheme may be utilized to sense the information stored on a multilevel cell. The more significant bit of the information in the cell may sense initially. The more significant bit information may be used to determine which of at least two reference levels to utilize to determine a less significant bit of the cell.
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公开(公告)号：US07106626B2
公开(公告)日：2006-09-12
申请号：US11196026
申请日：2005-08-03
IPC分类号： G11C16/04
CPC分类号： G11C7/106 , G11C7/06 , G11C7/062 , G11C7/1051 , G11C7/1069 , G11C11/56 , G11C11/5642 , G11C2211/5642
摘要： In accordance with one embodiment, a serial sensing scheme may be utilized to sense the information stored on a multilevel cell. The more significant bit of the information in the cell may sense initially. The more significant bit information may be used to determine which of at least two reference levels to utilize to determine a less significant bit of the cell.
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公开(公告)号：US07304889B2
公开(公告)日：2007-12-04
申请号：US11493060
申请日：2006-07-26
IPC分类号： G11C11/34
CPC分类号： G11C7/106 , G11C7/06 , G11C7/062 , G11C7/1051 , G11C7/1069 , G11C11/56 , G11C11/5642 , G11C2211/5642
摘要： A serial sensing scheme may be utilized to sense the information stored on a multilevel cell. The more significant bit of the information in the cell may sense initially. The more significant bit information may be used to determine which of at least two reference levels to utilize to determine a less significant bit of the cell.
摘要翻译： 可以使用串行感测方案来感测存储在多电平单元上的信息。 单元中信息的更重要的位最初可能会感觉到。 可以使用更高有效比特信息来确定要用于确定小区的较低有效比特的至少两个参考等级中的哪一个。
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公开(公告)号：US20050265098A1
公开(公告)日：2005-12-01
申请号：US11196026
申请日：2005-08-03
CPC分类号： G11C7/106 , G11C7/06 , G11C7/062 , G11C7/1051 , G11C7/1069 , G11C11/56 , G11C11/5642 , G11C2211/5642
摘要： In accordance with one embodiment, a serial sensing scheme may be utilized to sense the information stored on a multilevel cell. The more significant bit of the information in the cell may sense initially. The more significant bit information may be used to determine which of at least two reference levels to utilize to determine a less significant bit of the cell.
摘要翻译： 根据一个实施例，可以使用串行感测方案来感测存储在多电平单元上的信息。 单元中信息的更重要的位最初可能会感觉到。 可以使用更高有效比特信息来确定要用于确定小区的较低有效比特的至少两个参考等级中的哪一个。
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公开(公告)号：US07116597B1
公开(公告)日：2006-10-03
申请号：US11026347
申请日：2004-12-30
IPC分类号： G11C7/02
摘要： The various embodiments of the present invention provide high precision reference devices, methods, and systems. A high precision reference device may include a plurality of reference cells to receive bias voltages and to provide a cell reference, and an averaging stage coupled to the reference cells to generate an average reference that is the average of the cell references. Other devices, methods, and systems are also claimed and described.
摘要翻译： 本发明的各种实施例提供了高精度的参考装置，方法和系统。 高精度参考装置可以包括多个参考单元以接收偏置电压并提供单元参考，以及耦合到参考单元以产生作为单元参考平均值的平均参考的平均级。 还要求和描述其他设备，方法和系统。
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公开(公告)号：US07418418B2
公开(公告)日：2008-08-26
申请号：US10167001
申请日：2002-06-11
申请人： Adam Wizon , Joseph M. Kochansky , Matthew Goldman
发明人： Adam Wizon , Joseph M. Kochansky , Matthew Goldman
IPC分类号： G06Q40/00
摘要： A computer-based system is disclosed for pricing fixed income securities which includes a tool for selecting a portfolio of fixed income securities stored in a portfolio database, a graphical user interface for designating a pricing method for a selected fixed income security in the selected portfolio using computer readable character strings, a processor for calculating the price of the selected fixed income security based upon the designated pricing method.
摘要翻译： 公开了一种基于计算机的系统来定价固定收益证券，其中包括选择存储在投资组合数据库中的固定收益证券投资组合的工具，用于指定所选择投资组合中选定的固定收益证券的定价方法的图形用户界面， 计算机可读字符串，用于基于指定的定价方法计算所选择的固定收入证券的价格的处理器。
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7.发明授权Method and apparatus for treatment of state confidence data retrieved from a non-volatile memory array 有权用于处理从非易失性存储器阵列检索的状态置信数据的方法和装置公开(公告)号：US09582357B2
公开(公告)日：2017-02-28
申请号：US13977012
申请日：2012-03-29
CPC分类号： G06F11/1068 , G06F11/1048 , G11C11/5642 , G11C16/26 , G11C16/34 , G11C2029/0411
摘要： Various embodiments are generally directed to an apparatus, method and other techniques to retrieve data from a non-volatile memory, and to read a memory cell of the non-volatile memory at a first set of sense conditions comprising a multiplicity of sense conditions. Embodiments also include an apparatus, method and other techniques to set a first set of bits in an encoded output, the first set of bits comprising a logical state bit to indicate a logical state of the memory cell and one or more additional bits in the encoded output to indicate accuracy of the logical state bit based upon results of the read at the first set of sense conditions, the first set of sense conditions comprising a greater number than that of the first set of bits.
摘要翻译： 各种实施例通常涉及从非易失性存储器检索数据的装置，方法和其他技术，以及在包括多个感测条件的第一组感测条件下读取非易失性存储器的存储器单元。 实施例还包括用于设置编码输出中的第一组位的装置，方法和其它技术，第一组位包括逻辑状态位以指示存储器单元的逻辑状态和编码的存储单元中的一个或多个附加位 输出以基于在第一组感测条件下的读取结果来指示逻辑状态位的精确度，第一组感测条件包括比第一组位数更大的数量。
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公开(公告)号：US09001577B2
公开(公告)日：2015-04-07
申请号：US13486767
申请日：2012-06-01
CPC分类号： G11C16/28 , G06F12/0875 , G06F2212/452 , G11C16/04 , G11C16/26 , G11C16/3427
摘要： This disclosure concerns memory cell sensing. One or more methods include determining a data state of a first memory cell coupled to a first data line, determining a data state of a third memory cell coupled to a third data line, transferring determined data of at least one of the first and the third memory cells to a data line control unit corresponding to a second data line to which a second memory cell is coupled, the second data line being adjacent to the first data line and the third data line, and determining a data state of the second memory cell based, at least partially, on the transferred determined data.
摘要翻译： 本公开涉及存储器单元感测。 一种或多种方法包括确定耦合到第一数据线的第一存储器单元的数据状态，确定耦合到第三数据线的第三存储器单元的数据状态，传送第一和第三数据线中的至少一个的确定数据 存储单元连接到与第二存储器单元耦合的第二数据线相对应的数据线控制单元，第二数据线与第一数据线和第三数据线相邻，并且确定第二存储器单元的数据状态 至少部分地基于所转移的确定的数据。
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公开(公告)号：US08595597B2
公开(公告)日：2013-11-26
申请号：US13039553
申请日：2011-03-03
申请人： Ningde Xie , Matthew Goldman , Jawad B. Khan , Robert W. Faber
发明人： Ningde Xie , Matthew Goldman , Jawad B. Khan , Robert W. Faber
CPC分类号： G06F11/1048 , G11C16/00 , G11C29/021 , G11C29/028 , G11C29/52 , G11C2029/0409 , G11C2029/0411
摘要： Embodiments of the invention describe methods, systems and apparatuses to improve solid state device (SSD) write speed by efficiently utilizing error correction code executed for the device. SSDs may be comprised of several NAND memory devices. It is understood that such devices tend to have a raw bit error rate (RBER) that is related to the program/erase cycle count for the device.Embodiments of the invention efficiently use system ECC by changing the operating conditions of the SSD to better utilize the robustness of the implemented ECC algorithm. For example, embodiments of the invention may alter the programming voltage supplied to an SSD to increase write speed; such an increase may increase the RBER of the device, but will not affect the accuracy of such operations due to the ECC that is provisioned for end of life storage fidelity (i.e., the RBER that will occur at the end of life).
摘要翻译： 本发明的实施例描述了通过有效利用为设备执行的纠错码来改善固态设备（SSD）写入速度的方法，系统和装置。 SSD可以由多个NAND存储器件组成。 应当理解，这样的设备倾向于具有与设备的编程/擦除周期计数相关的原始误码率（RBER）。 本发明的实施例通过改变SSD的操作条件来有效地使用系统ECC，以更好地利用所实施的ECC算法的鲁棒性。 例如，本发明的实施例可以改变提供给SSD的编程电压以增加写入速度; 这样的增加可能增加设备的RBER，但是由于为终端存储保真度（即，将在生命结束时发生的RBER）提供的ECC而不会影响这种操作的准确性。
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10.发明授权Apparatuses and methods for pre-charging intermediate nodes for high-speed wordline 有权用于为高速字线预充电中间节点的装置和方法公开(公告)号：US07139205B1
公开(公告)日：2006-11-21
申请号：US11026510
申请日：2004-12-30
IPC分类号： G11C7/00
CPC分类号： G11C8/08
摘要： An apparatus and method for pre-charging an intermediate node for high-speed wordlines for accessing memory cells in high-speed memory arrays. The apparatus pre-charges a local capacitance located between a wordline supply voltage and the wordline to a voltage level that is greater than the wordline supply voltage. Once the wordline is selected, the charge stored on the local capacitance may be quickly shared with the capacitance of the wordline. The wordline supply voltage may be applied to the local capacitance to provide small, incremental voltage to move the wordline to its final voltage thereby improving the response time of the system.
摘要翻译： 一种用于对用于访问高速存储器阵列中的存储器单元的高速字线预充电中间节点的装置和方法。 该设备将位于字线电源电压和字线之间的本地电容预充电至大于字线电源电压的电压电平。 一旦选择了字线，存储在本地电容上的电荷可以与字线的电容快速共享。 可以将字线电源电压施加到本地电容以提供小的增量电压以将字线移动到其最终电压，从而提高系统的响应时间。
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