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    Memory cell sensing
    2.
    发明授权
    Memory cell sensing 有权
    记忆单元感应

    公开(公告)号：US09001577B2

    公开(公告)日：2015-04-07

    申请号：US13486767

    申请日：2012-06-01

    申请人： Matthew Goldman ,  Pranav Kalavade ,  Uday Chandrasekhar ,  Mark A. Helm

    发明人： Matthew Goldman ,  Pranav Kalavade ,  Uday Chandrasekhar ,  Mark A. Helm

    IPC分类号： G11C11/34 ,  G11C16/04 ,  G11C16/26 ,  G11C16/28 ,  G11C16/34

    CPC分类号： G11C16/28 ,  G06F12/0875 ,  G06F2212/452 ,  G11C16/04 ,  G11C16/26 ,  G11C16/3427

    摘要： This disclosure concerns memory cell sensing. One or more methods include determining a data state of a first memory cell coupled to a first data line, determining a data state of a third memory cell coupled to a third data line, transferring determined data of at least one of the first and the third memory cells to a data line control unit corresponding to a second data line to which a second memory cell is coupled, the second data line being adjacent to the first data line and the third data line, and determining a data state of the second memory cell based, at least partially, on the transferred determined data.

    摘要翻译： 本公开涉及存储器单元感测。 一种或多种方法包括确定耦合到第一数据线的第一存储器单元的数据状态，确定耦合到第三数据线的第三存储器单元的数据状态，传送第一和第三数据线中的至少一个的确定数据 存储单元连接到与第二存储器单元耦合的第二数据线相对应的数据线控制单元，第二数据线与第一数据线和第三数据线相邻，并且确定第二存储器单元的数据状态 至少部分地基于所转移的确定的数据。

    Methods, devices, and systems for data sensing in a memory system
    5.
    发明授权
    Methods, devices, and systems for data sensing in a memory system 有权
    用于存储系统中数据传感的方法，设备和系统

    公开(公告)号：US08631288B2

    公开(公告)日：2014-01-14

    申请号：US13047555

    申请日：2011-03-14

    申请人： Mark A. Helm ,  Uday Chandrasekhar

    发明人： Mark A. Helm ,  Uday Chandrasekhar

    IPC分类号： G11C29/00

    CPC分类号： G11C16/28 ,  G06F11/10 ,  G06F11/1008 ,  G06F11/1068 ,  G11C16/3454 ,  G11C29/52 ,  H03M13/03 ,  H03M13/05

    摘要： Methods, devices, and systems for data sensing in a memory system can include performing a number of successive sense operations on a number of memory cells using a number of different sensing voltages, determining a quantity of the number memory cells that change states between consecutive sense operations of the number of successive sense operations, and determining, based at least partially on the determined quantity of the number of memory cells that change states between consecutive sense operations, whether to output hard data corresponding to one of the number of successive sense operations.

    摘要翻译： 存储器系统中用于数据感测的方法，设备和系统可以包括使用多个不同感测电压对多个存储器单元执行多个连续感测操作，确定在连续感测之间改变状态的数量存储器单元的数量 至少部分地确定在连续感测操作之间改变状态的存储器单元的数量的确定量，是否输出对应于多个连续感测操作之一的硬数据的操作。

    METHODS, DEVICES, AND SYSTEMS FOR DATA SENSING
    6.
    发明申请
    METHODS, DEVICES, AND SYSTEMS FOR DATA SENSING 有权
    用于数据传感的方法，设备和系统

    公开(公告)号：US20120240011A1

    公开(公告)日：2012-09-20

    申请号：US13047555

    申请日：2011-03-14

    申请人： Mark A. Helm ,  Uday Chandrasekhar

    发明人： Mark A. Helm ,  Uday Chandrasekhar

    IPC分类号： G11C16/28 ,  G06F11/10 ,  H03M13/05

    CPC分类号： G11C16/28 ,  G06F11/10 ,  G06F11/1008 ,  G06F11/1068 ,  G11C16/3454 ,  G11C29/52 ,  H03M13/03 ,  H03M13/05

    摘要： The present disclosure includes methods and devices for data sensing. One such method includes performing a number of successive sense operations on a number of memory cells using a number of different sensing voltages, determining a quantity of the number memory cells that change states between consecutive sense operations of the number of successive sense operations, and determining, based at least partially on the determined quantity of the number of memory cells that change states between consecutive sense operations, whether to output hard data corresponding to one of the number of successive sense operations.

    摘要翻译： 本公开包括用于数据感测的方法和装置。 一种这样的方法包括使用多个不同感测电压对多个存储器单元执行多个连续感测操作，确定在连续感测操作的数量的连续感测操作之间改变状态的数量存储器单元的数量，以及确定 至少部分地基于确定在连续感测操作之间改变状态的存储器单元的数量的确定数量，是否输出对应于多个连续感测操作中的一个的硬数据。

    MEMORY DEVICES AND OPERATING METHODS FOR A MEMORY DEVICE
    7.
    发明申请
    MEMORY DEVICES AND OPERATING METHODS FOR A MEMORY DEVICE 有权
    用于存储器件的存储器件和操作方法

    公开(公告)号：US20140063937A1

    公开(公告)日：2014-03-06

    申请号：US13599208

    申请日：2012-08-30

    申请人： Matthew Goldman ,  Mark A. Helm ,  Jaydip B. Patel ,  Thomas F. Ryan

    发明人： Matthew Goldman ,  Mark A. Helm ,  Jaydip B. Patel ,  Thomas F. Ryan

    IPC分类号： G11C16/10 ,  G11C16/04

    CPC分类号： G11C16/0483 ,  G11C11/5628 ,  G11C16/10 ,  G11C2211/5622 ,  G11C2211/5641

    摘要： Devices and methods facilitate memory device operation in all bit line architecture memory devices. In at least one embodiment, memory cells comprising alternating rows are concurrently programmed by row and concurrently sensed by row at a first density whereas memory cells comprising different alternating rows are concurrently programmed by row and concurrently sensed by row at a second density. In at least one additional embodiment, memory cells comprising alternating tiers of memory cells are programmed and sensed by tier at a first density and memory cells comprising different alternating tiers of memory cells are programmed and sensed by tier at a second density.

    摘要翻译： 器件和方法便于存储器件在所有位线架构存储器件中的操作。 在至少一个实施例中，包括交替行的存储器单元同时由行编程并以第一密度由行同时感测，而包括不同交替行的存储单元同时由行编程并以第二密度由行同时检测。 在至少一个附加实施例中，包括交替层次的存储器单元的存储器单元以第一密度的层被编程和感测，并且包括不同交替层的存储器单元的存储单元由第二密度的层编程和感测。

    Memory devices and operating methods for a memory device
    8.
    发明授权
    Memory devices and operating methods for a memory device 有权
    存储器件的存储器件和操作方法

    公开(公告)号：US08902650B2

    公开(公告)日：2014-12-02

    申请号：US13599208

    申请日：2012-08-30

    申请人： Matthew Goldman ,  Mark A. Helm ,  Jaydip B. Patel ,  Thomas F. Ryan

    发明人： Matthew Goldman ,  Mark A. Helm ,  Jaydip B. Patel ,  Thomas F. Ryan

    IPC分类号： G11C16/04

    CPC分类号： G11C16/0483 ,  G11C11/5628 ,  G11C16/10 ,  G11C2211/5622 ,  G11C2211/5641

    摘要： Devices and methods facilitate memory device operation in all bit line architecture memory devices. In at least one embodiment, memory cells comprising alternating rows are concurrently programmed by row and concurrently sensed by row at a first density whereas memory cells comprising different alternating rows are concurrently programmed by row and concurrently sensed by row at a second density. In at least one additional embodiment, memory cells comprising alternating tiers of memory cells are programmed and sensed by tier at a first density and memory cells comprising different alternating tiers of memory cells are programmed and sensed by tier at a second density.

    摘要翻译： 器件和方法便于存储器件在所有位线架构存储器件中的操作。 在至少一个实施例中，包括交替行的存储器单元同时由行编程并以第一密度由行同时感测，而包括不同交替行的存储单元同时由行编程并且由第二密度同时检测。 在至少一个附加实施例中，包括交替层次的存储器单元的存储器单元以第一密度的层被编程和感测，并且包括不同交替层的存储器单元的存储单元由第二密度的层编程和感测。

    Method of forming an array of FLASH field effect transistors and circuitry peripheral to such array
    9.
    发明授权
    Method of forming an array of FLASH field effect transistors and circuitry peripheral to such array 有权
    形成FLASH场效应晶体管阵列和这种阵列外围电路的方法

    公开(公告)号：US06746921B2

    公开(公告)日：2004-06-08

    申请号：US10179893

    申请日：2002-06-24

    申请人： Roger W Lindsay ,  Mark A. Helm

    发明人： Roger W Lindsay ,  Mark A. Helm

    IPC分类号： H01L21336

    CPC分类号： H01L27/11526 ,  H01L27/105 ,  H01L27/11543

    摘要： Thermal oxidation of a peripheral area of a semiconductor substrate is globally restricted with an overlying oxidation resistant layer that is not globally received within the array during formation of a sacrificial oxide layer prior to forming any transistor gate dielectric layer within the array. At least some FLASH field effect transistor gates having floating gate dielectric of a first thickness are formed within the array and at least some non-FLASH field effect transistor gates having gate dielectric of a second thickness are formed within the periphery, with the first and second thicknesses being different. Other aspects and implementations are disclosed.

    摘要翻译： 在形成阵列内的任何晶体管栅极电介质层之前，在形成牺牲氧化物层期间，覆盖抗氧化层在阵列内未被全局接收的情况下，全局限制半导体衬底的外围区域的热氧化。 至少一些具有第一厚度的浮置栅极电介质的FLASH场效应晶体管栅极形成在阵列内，并且至少一些具有第二厚度的栅极电介质的非FLASH场效应晶体管栅极形成在外围，其中第一和第二 厚度不同。 公开了其他方面和实现。

    Efficient fabrication process for dual well type structures
    10.
    发明授权
    Efficient fabrication process for dual well type structures 失效
    双井型结构的高效制造工艺

    公开(公告)号：US06396100B2

    公开(公告)日：2002-05-28

    申请号：US09901035

    申请日：2001-07-10

    申请人： Mark A. Helm

    发明人： Mark A. Helm

    IPC分类号： H01L29788

    CPC分类号： H01L21/823842 ,  H01L21/823857 ,  H01L21/823892

    摘要： An efficient method for fabricating dual well type structures uses the same number of masks used in single well type structure fabrication. In a preferred embodiment, the current invention allows low voltage and high voltage n-channel transistors and low voltage and high voltage p-channel transistors to be formed in a single substrate. One mask is used for forming a diffusion well, a second mask for both forming a retrograde well and doping the well to achieve an intermediate threshold voltage in that well, and a third mask for both differentiating the gate oxides for the low voltage devices and doping the threshold voltages to achieve the final threshold voltages.

    摘要翻译： 用于制造双井型结构的有效方法使用在单井型结构制造中使用的相同数量的掩模。 在优选实施例中，本发明允许在单个衬底中形成低电压和高电压n沟道晶体管，并且低电压和高压p沟道晶体管形成。 用于形成扩散阱的一个掩模，用于形成逆行阱并掺杂阱以在该阱中实现中间阈值电压的第二掩模，以及用于区分低电压器件的栅极氧化物和掺杂的第三掩模 阈值电压以达到最终阈值电压。