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公开(公告)号：US20130322170A1
公开(公告)日：2013-12-05
申请号：US13486767
申请日：2012-06-01
CPC分类号： G11C16/28 , G06F12/0875 , G06F2212/452 , G11C16/04 , G11C16/26 , G11C16/3427
摘要： This disclosure concerns memory cell sensing. One or more methods include determining a data state of a first memory cell coupled to a first data line, determining a data state of a third memory cell coupled to a third data line, transferring determined data of at least one of the first and the third memory cells to a data line control unit corresponding to a second data line to which a second memory cell is coupled, the second data line being adjacent to the first data line and the third data line, and determining a data state of the second memory cell based, at least partially, on the transferred determined data.
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公开(公告)号：US09001577B2
公开(公告)日：2015-04-07
申请号：US13486767
申请日：2012-06-01
CPC分类号： G11C16/28 , G06F12/0875 , G06F2212/452 , G11C16/04 , G11C16/26 , G11C16/3427
摘要： This disclosure concerns memory cell sensing. One or more methods include determining a data state of a first memory cell coupled to a first data line, determining a data state of a third memory cell coupled to a third data line, transferring determined data of at least one of the first and the third memory cells to a data line control unit corresponding to a second data line to which a second memory cell is coupled, the second data line being adjacent to the first data line and the third data line, and determining a data state of the second memory cell based, at least partially, on the transferred determined data.
摘要翻译： 本公开涉及存储器单元感测。 一种或多种方法包括确定耦合到第一数据线的第一存储器单元的数据状态，确定耦合到第三数据线的第三存储器单元的数据状态，传送第一和第三数据线中的至少一个的确定数据 存储单元连接到与第二存储器单元耦合的第二数据线相对应的数据线控制单元，第二数据线与第一数据线和第三数据线相邻，并且确定第二存储器单元的数据状态 至少部分地基于所转移的确定的数据。
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公开(公告)号：US20190043563A1
公开(公告)日：2019-02-07
申请号：US16146814
申请日：2018-09-28
IPC分类号： G11C11/56
CPC分类号： G11C11/5628 , G11C11/5642 , G11C16/0483 , G11C16/3459 , G11C2211/561 , G11C2211/5621
摘要： An apparatus and/or system is described including a memory device or a controller to perform programming and verification operations including application of a shared voltage level to verify two program voltage levels of a multi-level cell device. For example, in embodiments, the control circuitry performs a program operation to program a memory cell and performs a verification operation by applying a single or shared verify voltage level to verify that the memory cell is programmed to a corresponding program voltage level. In embodiments, the program voltage level is one of two consecutive program voltage levels of a plurality of program voltage levels to be verified by application of the shared verify voltage. Other embodiments are disclosed and claimed.
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公开(公告)号：US20120117306A1
公开(公告)日：2012-05-10
申请号：US12942152
申请日：2010-11-09
申请人： Shafqat Ahmed , Khaled Hasnat , Pranav Kalavade , Krishna Parat , Aaron Yip , Mark A. Helm , Andrew Bicksler
发明人： Shafqat Ahmed , Khaled Hasnat , Pranav Kalavade , Krishna Parat , Aaron Yip , Mark A. Helm , Andrew Bicksler
CPC分类号： G06F3/0625 , G06F3/061 , G06F3/0653 , G06F3/0665 , G06F3/0688 , G06F3/0689 , G06F12/0804 , G06F12/0846 , G06F13/28 , G06F2212/2022 , G06F2212/224 , G06F2212/461 , G11C16/0483 , G11C16/24 , G11C16/26 , Y02D10/14
摘要： Memory devices, methods for programming sense flags, methods for sensing flags, and memory systems are disclosed. In one such memory device, the odd bit lines of a flag memory cell array are connected with a short circuit to a dynamic data cache. The even bit lines of the flag memory cell array are disconnected from the dynamic data cache. When an even page of a main memory cell array is read, the odd flag memory cells, comprising flag data, are read at the same time so that it can be determined whether the odd page of the main memory cell array has been programmed. If the flag data indicates that the odd page has not been programmed, threshold voltage windows can be adjusted to determine the states of the sensed even memory cell page.
摘要翻译： 公开了存储器件，用于编程感测标志的方法，用于感测标志的方法和存储器系统。 在一个这样的存储器件中，标志存储器单元阵列的奇数位线与短路连接到动态数据高速缓存。 标记存储单元阵列的偶数位线与动态数据高速缓存断开连接。 当读取主存储单元阵列的偶数页时，同时读取包括标志数据的奇数标志存储单元，以便可以确定主存储单元阵列的奇数页是否已被编程。 如果标志数据指示奇数页未被编程，则可以调整阈值电压窗口以确定感测到的偶数存储单元页的状态。
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公开(公告)号：US09135998B2
公开(公告)日：2015-09-15
申请号：US12942152
申请日：2010-11-09
申请人： Shafqat Ahmed , Khaled Hasnat , Pranav Kalavade , Krishna Parat , Aaron Yip , Mark A. Helm , Andrew Bicksler
发明人： Shafqat Ahmed , Khaled Hasnat , Pranav Kalavade , Krishna Parat , Aaron Yip , Mark A. Helm , Andrew Bicksler
CPC分类号： G06F3/0625 , G06F3/061 , G06F3/0653 , G06F3/0665 , G06F3/0688 , G06F3/0689 , G06F12/0804 , G06F12/0846 , G06F13/28 , G06F2212/2022 , G06F2212/224 , G06F2212/461 , G11C16/0483 , G11C16/24 , G11C16/26 , Y02D10/14
摘要： Memory devices, methods for programming sense flags, methods for sensing flags, and memory systems are disclosed. In one such memory device, the odd bit lines of a flag memory cell array are connected with a short circuit to a dynamic data cache. The even bit lines of the flag memory cell array are disconnected from the dynamic data cache. When an even page of a main memory cell array is read, the odd flag memory cells, comprising flag data, are read at the same time so that it can be determined whether the odd page of the main memory cell array has been programmed. If the flag data indicates that the odd page has not been programmed, threshold voltage windows can be adjusted to determine the states of the sensed even memory cell page.
摘要翻译： 公开了存储器件，用于编程感测标志的方法，用于感测标志的方法和存储器系统。 在一个这样的存储器件中，标志存储器单元阵列的奇数位线与短路连接到动态数据高速缓存。 标记存储单元阵列的偶数位线与动态数据高速缓存断开连接。 当读取主存储单元阵列的偶数页时，同时读取包括标志数据的奇数标志存储单元，以便可以确定主存储单元阵列的奇数页是否已被编程。 如果标志数据指示奇数页未被编程，则可以调整阈值电压窗口以确定感测到的偶数存储单元页的状态。
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6.发明申请METHOD AND SYSTEM TO OBTAIN STATE CONFIDENCE DATA USING MULTISTROBE READ OF A NON-VOLATILE MEMORY 有权使用多列读取非易失性存储器来获取状态数据的方法和系统公开(公告)号：US20140380108A1
公开(公告)日：2014-12-25
申请号：US13977011
申请日：2012-03-29
CPC分类号： G11C29/50004 , G06F11/1048 , G06F11/1068 , G11C11/5642 , G11C16/26 , G11C16/34 , G11C2029/0411 , G11C2029/5004
摘要： An apparatus may include a processor circuit a processor circuit to retrieve data from a non-volatile memory, and a multistrobe read module operable on the processor circuit to set a read operation to read a memory cell over a multiplicity of sense operations, where each sense operation is performed under a different sense condition. The multistrobe read module may be further operable to schedule a new sense operation to succeed a prior sense operation of the multiplicity of sense operations without recharge of the wordline when a value of one or more read condition is within a preset range. Other embodiments are disclosed and claimed.
摘要翻译： 一种装置可以包括处理器电路，用于从非易失性存储器检索数据，以及多处理器读取模块，其可在所述处理器电路上操作以设置读取操作以在多种感测操作上读取存储器单元， 在不同的感测条件下进行操作。 当一个或多个读取条件的值处于预设范围内时，该多画面读取模块还可以进一步操作，以调度新的感测操作，从而在许多感测操作的先前感测操作中继续进行，而不对字线进行再充电。 公开和要求保护其他实施例。
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7.发明授权公开(公告)号：US09754683B2
公开(公告)日：2017-09-05
申请号：US13977011
申请日：2012-03-29
CPC分类号： G11C29/50004 , G06F11/1048 , G06F11/1068 , G11C11/5642 , G11C16/26 , G11C16/34 , G11C2029/0411 , G11C2029/5004
摘要： An apparatus may include a processor circuit a processor circuit to retrieve data from a non-volatile memory, and a multistrobe read module operable on the processor circuit to set a read operation to read a memory cell over a multiplicity of sense operations, where each sense operation is performed under a different sense condition. The multistrobe read module may be further operable to schedule a new sense operation to succeed a prior sense operation of the multiplicity of sense operations without recharge of the wordline when a value of one or more read condition is within a preset range. Other embodiments are disclosed and claimed.
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公开(公告)号：US20150179267A1
公开(公告)日：2015-06-25
申请号：US14139219
申请日：2013-12-23
CPC分类号： G11C11/5642 , G11C11/5628 , G11C16/0483 , G11C16/08 , G11C16/10 , G11C16/107 , G11C16/28 , G11C16/3454
摘要： Embodiments of methods and systems disclosed herein provide a NAND cell programming technique that results in a substantially reduced Tprog to complete a programming operation. In particular, embodiments of the subject matter disclosed herein utilize two Vpgm programming pulses during each programming iteration, or loop. One of the two programming pulses corresponds to a conventional programming Vpgm pulse and the second pulse comprises a programming pulse that having a greater Vpgm that is greater than the conventional programming Vpgm so that the slow cells are programmed to PV in fewer pulses (iterations), thereby effectively simultaneously programming and verifying cells having different programming speeds.
摘要翻译： 本文公开的方法和系统的实施例提供NAND单元编程技术，其导致基本上减少的T程序以完成编程操作。 特别地，本文公开的主题的实施例在每个编程迭代期间利用两个Vpgm编程脉冲或循环。 两个编程脉冲之一对应于常规编程Vpgm脉冲，第二脉冲包括具有比常规编程Vpgm更大的Vpgm的编程脉冲，使得慢单元以更少的脉冲（迭代）被编程为PV， 从而有效地同时编程和验证具有不同编程速度的单元。
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公开(公告)号：US08411508B2
公开(公告)日：2013-04-02
申请号：US12573579
申请日：2009-10-05
申请人： Pranav Kalavade , Krishna K. Parat , Paul D. Ruby
发明人： Pranav Kalavade , Krishna K. Parat , Paul D. Ruby
IPC分类号： G11C11/34
CPC分类号： G11C16/12 , G11C11/5628 , G11C16/0483 , G11C16/3454 , G11C16/3459 , G11C2211/5621
摘要： Apparatus, methods, and systems are disclosed, including those to improve program voltage distribution width using automatic selective slow program convergence (ASSPC). One such method may include determining whether a threshold voltage (Vt) associated with a memory cell has reached a particular pre-program verify voltage. In response to the determination, a voltage applied to a bit-line coupled to the memory cell may be automatically incremented at least twice as the program voltage is increased, until the cell is properly programmed. Additional embodiments are also described.
摘要翻译： 公开了装置，方法和系统，包括使用自动选择性慢程序融合（ASSPC）来提高编程电压分配宽度的装置，方法和系统。 一种这样的方法可以包括确定与存储器单元相关联的阈值电压（Vt）是否已经达到特定的预编程验证电压。 响应于该确定，施加到耦合到存储器单元的位线的电压可以自动递增至少两倍于编程电压增加，直到单元被适当地编程为止。 还描述了另外的实施例。
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公开(公告)号：US08248862B2
公开(公告)日：2012-08-21
申请号：US12636896
申请日：2009-12-14
IPC分类号： G11C7/00
CPC分类号： G11C5/145 , G11C11/5628 , G11C11/5678 , G11C13/0004 , G11C13/0038 , G11C16/0483 , G11C16/30
摘要： The threshold voltage range of a multilevel memory cell may be increased without using a negative voltage pump. In one embodiment, an added positive voltage may be applied to the source of the selected cell. A boost voltage may be applied to the output of a sense amplifier. Non-ideal characteristics of a buffer that supplies the voltage to the selected cell may be compensated for in some embodiments.
摘要翻译： 可以在不使用负电压泵的情况下增加多电平存储器单元的阈值电压范围。 在一个实施例中，可以向所选择的单元的源施加附加的正电压。 升压电压可以被施加到读出放大器的输出。 在一些实施例中，可以补偿向所选择的单元提供电压的缓冲器的非理想特性。
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