-
公开(公告)号：US6030453A
公开(公告)日：2000-02-29
申请号：US812950
申请日：1997-03-04
IPC分类号： H01L21/205 , H01L21/02 , H01L21/31 , H01L21/316 , C30B23/02
CPC分类号： H01L21/31604
摘要： A production process for protecting the surface of compound semiconductor wafers includes providing a multi-wafer epitaxial production system with a transfer and load module, a III-V growth chamber and an insulator chamber. The wafer is placed in the transfer and load module and the pressure is reduced to .ltoreq.10.sup.-10 Torr, after which the wafer is moved to the III-V growth chamber and layers of compound semiconductor material are epitaxially grown on the surface of the wafer. The wafer is then moved through the transfer and load module to the insulator chamber and an insulating cap layer is formed by thermally evaporating gallium oxide molecules from an effusion cell using an evaporation source in an oxide crucible, which oxide crucible does not form an eutectic alloy with the evaporation source
摘要翻译： 用于保护化合物半导体晶片的表面的制造方法包括提供具有传输和负载模块，III-V生长室和绝缘体室的多晶片外延生产系统。 将晶片放置在传送和加载模块中，并将压力降低到10-10托，之后将晶片移动到III-V生长室，并且将化合物半导体材料层外延生长在 晶圆。 然后将晶片通过传输和负载模块移动到绝缘体室，并且通过使用氧化物坩埚中的蒸发源从渗出电池热蒸发氧化镓分子而形成绝缘盖层，该氧化物坩埚不形成共晶合金 与蒸发源
-
2.发明授权Fabrication method for a gate quality oxide-compound semiconductor structure 失效栅极质量氧化物 - 半导体结构的制造方法
公开(公告)号：US5904553A
公开(公告)日：1999-05-18
申请号：US917119
申请日：1997-08-25
IPC分类号： C23C16/40 , C23C16/44 , C23C16/455 , H01L21/316 , H01L21/3205 , H01L21/4763
CPC分类号： C23C16/45523 , C23C16/407 , C23C16/455 , C23C16/4551 , H01L21/31604
摘要： A method of fabricating a gate quality oxide-compound semiconductor structure includes forming an insulating Ga.sub.2 O.sub.3 layer on the surface of a compound semiconductor wafer structure by a supersonic gas jet containing gallium oxide molecules and oxygen. In a preferred embodiment, a III-V compound semiconductor wafer structure with an atomically ordered and chemically clean semiconductor surface is transferred from a semiconductor growth chamber into an insulator deposition chamber via an ultra high vacuum preparation chamber. Ga.sub.2 O.sub.3 deposition onto the surface of the wafer structure is initiated by a supersonic gas jet pulse and proceeds via optimization of pulse duration, speed of gas jet, mole fraction of gallium oxide molecules and oxygen atoms, and plasma energy.
摘要翻译： 制造栅极质量氧化物半导体结构的方法包括通过含有氧化镓分子和氧的超音速气体射流在化合物半导体晶片结构的表面上形成绝缘Ga 2 O 3层。 在优选实施例中，具有原子级和化学清洁的半导体表面的III-V族化合物半导体晶片结构经由超高真空准备室从半导体生长室转移到绝缘体沉积室中。 通过超音速气体喷射脉冲引发晶片结构表面上的Ga 2 O 3沉积，并且经历脉冲持续时间，气体射流速度，氧化镓分子和氧原子的摩尔分数以及等离子体能量的优化。
-
公开(公告)号：US5907792A
公开(公告)日：1999-05-25
申请号：US917122
申请日：1997-08-25
IPC分类号： C23C14/06 , H01L21/318 , H01L29/78
CPC分类号： C23C14/0652 , H01L21/3185 , Y10S148/169 , Y10S438/961
摘要： A method of forming a silicon nitride layer or film on a semiconductor wafer structure includes forming a silicon nitride layer on the surface of a wafer structure using a molecular beam of high purity elemental Si and an atomic beam of high purity nitrogen. In a preferred embodiment, a III-V compound semiconductor wafer structure is heated in an ultra high vacuum system to a temperature below the decomposition temperature of said compound semiconductor wafer structure and a silicon nitride layer is formed using a molecular beam of Si provided by either thermal evaporation or electron beam evaporation, and an atomic nitrogen beam provided by either RF or microwave plasma discharge.
摘要翻译： 在半导体晶片结构上形成氮化硅层或膜的方法包括使用高纯度元素Si的分子束和高纯氮原子束在晶片结构的表面上形成氮化硅层。 在优选实施例中，III-V族化合物半导体晶片结构在超高真空系统中被加热至低于所述化合物半导体晶片结构的分解温度的温度，并且使用由以下两者之一提供的Si的分子束形成氮化硅层 热蒸发或电子束蒸发，以及由RF或微波等离子体放电提供的原子氮光束。
-
公开(公告)号：US08847280B2
公开(公告)日：2014-09-30
申请号：US13293910
申请日：2011-11-10
IPC分类号： H01L29/78 , H01L23/31 , H01L29/778 , H01L29/51 , H01L29/207
CPC分类号： H01L29/7783 , H01L23/3192 , H01L29/207 , H01L29/513 , H01L2924/0002 , H01L2924/12044 , H01L2924/13091 , H01L2924/00
摘要： An improved insulated gate field effect device is obtained by providing a substrate desirably comprising a III-V semiconductor, having a further semiconductor layer on the substrate adapted to contain the channel of the device between spaced apart source-drain electrodes formed on the semiconductor layer. A dielectric layer is formed on the semiconductor layer. A sealing layer is formed on the dielectric layer and exposed to an oxygen plasma. A gate electrode is formed on the dielectric layer between the source-drain electrodes. The dielectric layer preferably comprises gallium-oxide and/or gadolinium-gallium oxide, and the oxygen plasma is preferably an inductively coupled plasma. A further sealing layer of, for example, silicon nitride is desirably provided above the sealing layer. Surface states and gate dielectric traps that otherwise adversely affect leakage and channel sheet resistance are much reduced.
摘要翻译： 通过提供期望地包括III-V半导体的衬底来获得改进的绝缘栅场效应器件，所述衬底在衬底上具有另外的半导体层，其适于在形成在半导体层上的间隔开的源 - 漏电极之间容纳器件的沟道。 在半导体层上形成介电层。 在电介质层上形成密封层并暴露于氧等离子体。 在源 - 漏电极之间的电介质层上形成栅电极。 电介质层优选包含氧化镓和/或钆 - 镓氧化物，氧等离子体优选为电感耦合等离子体。 希望在密封层的上方设置另外的例如氮化硅的密封层。 否则对泄漏和通道薄层电阻有不利影响的表面状态和栅极电介质阱将大大减少。
-
公开(公告)号：US08105925B2
公开(公告)日：2012-01-31
申请号：US12182349
申请日：2008-07-30
IPC分类号： H01L21/26
CPC分类号： H01L29/7783 , H01L23/3192 , H01L29/207 , H01L29/513 , H01L2924/0002 , H01L2924/12044 , H01L2924/13091 , H01L2924/00
摘要： An improved insulated gate field effect device (60) is obtained by providing a substrate (20) desirably comprising a III-V semiconductor, having a further semiconductor layer (22) on the substrate (20) adapted to contain the channel (230) of the device (60) between spaced apart source-drain electrodes (421, 422) formed on the semiconductor layer (22). A dielectric layer (24) is formed on the semiconductor layer (22). A sealing layer (28) is formed on the dielectric layer (24) and exposed to an oxygen plasma (36). A gate electrode (482) is formed on the dielectric layer (24) between the source-drain electrodes (421, 422). The dielectric layer (24) preferably comprises gallium-oxide (25) and/or gadolinium-gallium oxide (26, 27), and the oxygen plasma (36) is preferably an inductively coupled plasma. A further sealing layer (44) of, for example, silicon nitride is desirably provided above the sealing layer (28). Surface states and gate dielectric traps that otherwise adversely affect leakage and channel sheet resistance are much reduced.
摘要翻译： 通过提供期望地包括III-V半导体的衬底（20）来获得改进的绝缘栅场效应器件（60），所述衬底（20）在所述衬底（20）上具有另外的半导体层（22），所述半导体层适于容纳所述沟道（230） 所述器件（60）形成在所述半导体层（22）上形成的间隔开的源 - 漏电极（421,422）之间。 在半导体层（22）上形成介电层（24）。 密封层（28）形成在电介质层（24）上并暴露于氧等离子体（36）。 在源漏电极（421,422）之间的电介质层（24）上形成栅电极（482）。 电介质层（24）优选包含氧化镓（25）和/或氧化钆 - 氧化镓（26,27），氧等离子体（36）优选为电感耦合等离子体。 期望地在密封层（28）的上方设置例如氮化硅的另外的密封层（44）。 否则对泄漏和通道薄层电阻有不利影响的表面状态和栅极电介质阱将大大减少。
-
公开(公告)号：US07842587B2
公开(公告)日：2010-11-30
申请号：US12022942
申请日：2008-01-30
申请人： Matthias Passlack , Jonathan K. Abrokwah , Karthik Rajagopalan , Haiping Zhou , Richard J. Hill , Xu Li , David A. Moran , Iain G. Thayne , Peter Zurcher
发明人： Matthias Passlack , Jonathan K. Abrokwah , Karthik Rajagopalan , Haiping Zhou , Richard J. Hill , Xu Li , David A. Moran , Iain G. Thayne , Peter Zurcher
IPC分类号： H01L21/20
CPC分类号： H01L29/78 , H01L29/20 , H01L29/66462 , H01L29/7785
摘要： A semiconductor fabrication process includes forming a gate dielectric layer (120) overlying a substrate (101) that includes a III-V semiconductor compound. The gate dielectric layer is patterned to produce a gate dielectric structure (121) that has a substantially vertical sidewall (127), e.g., a slope of approximately 45° to 90°. A metal contact structure (130) is formed overlying the wafer substrate. The contact structure is laterally displaced from the gate dielectric structure sufficiently to define a gap (133) between the two. The wafer (100) is heat treated, which causes migration of at least one of the metal elements to form an alloy region (137) in the underlying wafer substrate. The alloy region underlies the contact structure and extends across all or a portion of the wafer substrate underlying the gap. An insulative or dielectric capping layer (140,150) is then formed overlying the wafer and covering the portion of the substrate exposed by the gap.
摘要翻译： 半导体制造工艺包括形成覆盖在包括III-V半导体化合物的衬底（101）上的栅极电介质层（120）。 栅极介电层被图案化以产生具有基本上垂直的侧壁（127）的栅极电介质结构（121），例如大约45°至90°的斜率。 金属接触结构（130）形成在晶片衬底上。 接触结构被充分地从栅极电介质结构侧向移位以限定两者之间的间隙（133）。 对晶片（100）进行热处理，这导致至少一种金属元素迁移，从而在下面的晶片衬底中形成合金区域（137）。 合金区域位于接触结构的下面，并且延伸穿过位于间隙下方的晶片衬底的全部或一部分。 然后形成绝缘或介电覆盖层（140,150），覆盖晶片并覆盖由间隙暴露的衬底的部分。
-
公开(公告)号：US6025281A
公开(公告)日：2000-02-15
申请号：US993603
申请日：1997-12-18
申请人： Matthias Passlack , Jonathan K. Abrokwah , Sandeep Pendharkar , Stephen B. Clemens , Jimmy Z. Yu , Brian Bowers
发明人： Matthias Passlack , Jonathan K. Abrokwah , Sandeep Pendharkar , Stephen B. Clemens , Jimmy Z. Yu , Brian Bowers
IPC分类号： H01L21/28 , H01L21/30 , H01L21/3105 , H01L21/316
CPC分类号： H01L21/28264 , H01L21/3006 , H01L21/3105
摘要： A method of passivating interface states of oxide-compound semiconductor interfaces using molecular, atomic, or isotopic species wherein said species are applied before oxide deposition in ultra-high vacuum, or during interruption of oxide deposition in ultra-high vacuum (preferentially after oxide surface coverage of a submonolayer, a monolayer, or a few monolayers), or during oxide deposition in ultra-high vacuum, or after completion of oxide deposition, or before or after any processing steps of the as deposited interface structure. In a preferred embodiment, hydrogen or deuterium atoms are applied to a Ga.sub.2 O.sub.3 --GaAs interface at some point before, during, or after oxide deposition in ultra-high vacuum, or before or after any processing steps of the as deposited interface structure, at any given and useful substrate temperature wherein the atomic species can be provided by any one of RF discharge, microwave plasma discharge, or thermal dissociation.
摘要翻译： 使用分子，原子或同位素物质钝化氧化物 - 化合物半导体界面的界面状态的方法，其中所述物质在超高真空中的氧化物沉积之前或在超高真空（优选氧化物表面之后） 亚单层，单层或几个单层的覆盖），或者在超高真空中的氧化物沉积期间，或在氧化物沉积完成之后，或在作为沉积的界面结构的任何处理步骤之前或之后。 在一个优选的实施方案中，在超高真空中的氧化物沉积之前，期间或之后的某个时刻，或者在作为沉积的界面结构的任何处理步骤之前或之后，在任何时候，在任何时候，将氢或氘原子施加到Ga 2 O 3 -GaAs- 给定和有用的衬底温度，其中可以通过RF放电，微波等离子体放电或热解离中的任何一种来提供原子种类。
-
公开(公告)号：US20120056246A1
公开(公告)日：2012-03-08
申请号：US13293910
申请日：2011-11-10
IPC分类号： H01L29/78
CPC分类号： H01L29/7783 , H01L23/3192 , H01L29/207 , H01L29/513 , H01L2924/0002 , H01L2924/12044 , H01L2924/13091 , H01L2924/00
摘要： An improved insulated gate field effect device is obtained by providing a substrate desirably comprising a III-V semiconductor, having a further semiconductor layer on the substrate adapted to contain the channel of the device between spaced apart source-drain electrodes formed on the semiconductor layer. A dielectric layer is formed on the semiconductor layer. A sealing layer is formed on the dielectric layer and exposed to an oxygen plasma. A gate electrode is formed on the dielectric layer between the source-drain electrodes. The dielectric layer preferably comprises gallium-oxide and/or gadolinium-gallium oxide, and the oxygen plasma is preferably an inductively coupled plasma. A further sealing layer of, for example, silicon nitride is desirably provided above the sealing layer. Surface states and gate dielectric traps that otherwise adversely affect leakage and channel sheet resistance are much reduced.
摘要翻译： 通过提供期望地包括III-V半导体的衬底来获得改进的绝缘栅场效应器件，所述衬底在衬底上具有另外的半导体层，其适于在形成在半导体层上的间隔开的源 - 漏电极之间容纳器件的沟道。 在半导体层上形成介电层。 在电介质层上形成密封层并暴露于氧等离子体。 在源 - 漏电极之间的电介质层上形成栅电极。 电介质层优选包含氧化镓和/或钆 - 镓氧化物，氧等离子体优选为电感耦合等离子体。 希望在密封层的上方设置另外的例如氮化硅的密封层。 否则对泄漏和通道薄层电阻有不利影响的表面状态和栅极电介质阱将大大减少。
-
公开(公告)号：US20090189252A1
公开(公告)日：2009-07-30
申请号：US12022942
申请日：2008-01-30
申请人： Matthias Passlack , Jonathan K. Abrokwah , Karthik Rajagopalan , Haiping Zhou , Richard J. Hill , Xu Li , David A. Moran , Iain G. Thayne , Peter Zurcher
发明人： Matthias Passlack , Jonathan K. Abrokwah , Karthik Rajagopalan , Haiping Zhou , Richard J. Hill , Xu Li , David A. Moran , Iain G. Thayne , Peter Zurcher
IPC分类号： H01L21/334 , H01L29/20
CPC分类号： H01L29/78 , H01L29/20 , H01L29/66462 , H01L29/7785
摘要： A semiconductor fabrication process includes forming a gate dielectric layer (120) overlying a substrate (101) that includes a III-V semiconductor compound. The gate dielectric layer is patterned to produce a gate dielectric structure (121) that has a substantially vertical sidewall (127), e.g., a slope of approximately 45° to 90°. A metal contact structure (130) is formed overlying the wafer substrate. The contact structure is laterally displaced from the gate dielectric structure sufficiently to define a gap (133) between the two. The wafer (100) is heat treated, which causes migration of at least one of the metal elements to form an alloy region (137) in the underlying wafer substrate. The alloy region underlies the contact structure and extends across all or a portion of the wafer substrate underlying the gap. An insulative or dielectric capping layer (140,150) is then formed overlying the wafer and covering the portion of the substrate exposed by the gap.
摘要翻译： 半导体制造工艺包括形成覆盖在包括III-V半导体化合物的衬底（101）上的栅极电介质层（120）。 栅极介电层被图案化以产生具有基本上垂直的侧壁（127）的栅极电介质结构（121），例如大约45°至90°的斜率。 金属接触结构（130）形成在晶片衬底上。 接触结构被充分地从栅极电介质结构侧向移位以限定两者之间的间隙（133）。 对晶片（100）进行热处理，这导致至少一种金属元素迁移，从而在下面的晶片衬底中形成合金区域（137）。 合金区域位于接触结构的下面，并且延伸穿过位于间隙下方的晶片衬底的全部或一部分。 然后形成绝缘或介电覆盖层（140,150），覆盖晶片并覆盖由间隙暴露的衬底的部分。
-
公开(公告)号：US06359294B1
公开(公告)日：2002-03-19
申请号：US08812952
申请日：1997-03-04
IPC分类号： H01L2976
CPC分类号： H01L29/517 , H01L21/28158 , H01L21/28264 , H01L29/66462 , H01L29/802
摘要： An insulator-compound semiconductor interface structure is disclosed including compound semiconductor material with a spacer layer of semiconductor material having a bandgap which is wider than the bandgap of the compound semiconductor material positioned on a surface of the compound semiconductor material and an insulating layer positioned on the spacer layer. Minimum and maximum thicknesses of the spacer layer are determined by the penetration of the carrier wave function into the spacer layer and by the desired device performance. In a specific embodiment, the interface structure is formed in a multi-wafer epitaxial production system including a transfer and load module with a III-V growth chamber attached and an insulator chamber attached.
摘要翻译： 公开了一种绝缘体 - 化合物半导体界面结构，其包括具有半导体材料的隔离层的化合物半导体材料，该间隔层具有比位于化合物半导体材料的表面上的化合物半导体材料的带隙宽的带隙和位于化合物半导体材料的表面上的绝缘层 间隔层。 间隔层的最小和最大厚度由载波函数穿入间隔层和所需器件性能决定。 在具体实施例中，界面结构形成在多晶片外延生产系统中，该系统包括连接有III-V生长室的传输和负载模块，并连接有绝缘体室。
-
-
-
-
-
-
-
-
-
搜索结果
66 条记录 (耗时 0.033 秒)
