-
公开(公告)号：US5907792A
公开(公告)日：1999-05-25
申请号：US917122
申请日：1997-08-25
IPC分类号： C23C14/06 , H01L21/318 , H01L29/78
CPC分类号： C23C14/0652 , H01L21/3185 , Y10S148/169 , Y10S438/961
摘要： A method of forming a silicon nitride layer or film on a semiconductor wafer structure includes forming a silicon nitride layer on the surface of a wafer structure using a molecular beam of high purity elemental Si and an atomic beam of high purity nitrogen. In a preferred embodiment, a III-V compound semiconductor wafer structure is heated in an ultra high vacuum system to a temperature below the decomposition temperature of said compound semiconductor wafer structure and a silicon nitride layer is formed using a molecular beam of Si provided by either thermal evaporation or electron beam evaporation, and an atomic nitrogen beam provided by either RF or microwave plasma discharge.
摘要翻译： 在半导体晶片结构上形成氮化硅层或膜的方法包括使用高纯度元素Si的分子束和高纯氮原子束在晶片结构的表面上形成氮化硅层。 在优选实施例中，III-V族化合物半导体晶片结构在超高真空系统中被加热至低于所述化合物半导体晶片结构的分解温度的温度，并且使用由以下两者之一提供的Si的分子束形成氮化硅层 热蒸发或电子束蒸发，以及由RF或微波等离子体放电提供的原子氮光束。
-
公开(公告)号：US6110840A
公开(公告)日：2000-08-29
申请号：US24148
申请日：1998-02-17
IPC分类号： C23C14/02 , C23C14/16 , H01L21/285 , H01L21/306 , H01L21/31
CPC分类号： B82Y30/00 , C23C14/021 , C23C14/16 , H01L21/28518 , H01L21/02043
摘要： A method of passivating the surface of a Si wafer is disclosed including the steps of cleaning the surface of the Si wafer and depositing an alkaline earth metal on the clean surface at a wafer temperature in a range of approximately 400.degree. C. to 750.degree. C. The surface is monitored during deposition to detect a (4.times.2) surface reconstruction pattern indicating approximately a one-quarter monolayer of alkaline earth metal is formed. The wafer is annealed at a temperature in a range of 800.degree. C. to 900.degree. C. until the alkaline earth metal forms an alkaline earth metal silicide with a (2.times.1) surface pattern on the surface.
摘要翻译： 公开了一种钝化Si晶片的表面的方法，包括以下步骤：在大约400℃至750℃的晶圆温度下清洁Si晶片的表面并在清洁表面上沉积碱土金属 在沉积期间监测表面以检测（4×2）表面重建图案，其指示形成大约四分之一的碱土金属单层。 将晶片在800℃至900℃的温度下进行退火，直到碱土金属在表面上形成具有（2x1）表面图案的碱土金属硅化物。
-
3.发明授权Method of preparing crystalline alkaline earth metal oxides on a Si substrate 失效在Si衬底上制备结晶碱土金属氧化物的方法
公开(公告)号：US6113690A
公开(公告)日：2000-09-05
申请号：US93081
申请日：1998-06-08
摘要： A method of preparing crystalline alkaline earth metal oxides on a Si substrate wherein a Si substrate with amorphous silicon dioxide on a surface is provided. The substrate is heated to a temperature in a range of 700.degree. C. to 800.degree. C. and exposed to a beam of alkaline earth metal(s) in a molecular beam epitaxy chamber at a pressure within approximately a 10.sup.-9 -10.sup.-10 Torr range. During the molecular beam epitaxy the surface is monitored by RHEED technique to determine a conversion of the amorphous silicon dioxide to a crystalline alkaline earth metal oxide. Once the alkaline earth metal oxide is formed, additional layers of material, e.g. additional thickness of an alkaline earth metal oxide, single crystal ferroelectrics or high dielectric constant oxides on silicon for non-volatile and high density memory device applications.
摘要翻译： 在Si衬底上制备结晶碱土金属氧化物的方法，其中提供了表面上具有无定形二氧化硅的Si衬底。 将基底加热至700℃至800℃的温度，并在分子束外延室内以大约10-9-10℃的压力暴露于一束或多束碱土金属， 10乇范围。 在分子束外延期间，通过RHEED技术监测表面以确定无定形二氧化硅向结晶碱土金属氧化物的转化。 一旦形成碱土金属氧化物，可以使用另外的材料层。 用于非易失性和高密度存储器件应用的碱土金属氧化物，单晶铁电体或硅上的高介电常数氧化物的附加厚度。
-
公开(公告)号：US06359294B1
公开(公告)日：2002-03-19
申请号：US08812952
申请日：1997-03-04
IPC分类号： H01L2976
CPC分类号： H01L29/517 , H01L21/28158 , H01L21/28264 , H01L29/66462 , H01L29/802
摘要： An insulator-compound semiconductor interface structure is disclosed including compound semiconductor material with a spacer layer of semiconductor material having a bandgap which is wider than the bandgap of the compound semiconductor material positioned on a surface of the compound semiconductor material and an insulating layer positioned on the spacer layer. Minimum and maximum thicknesses of the spacer layer are determined by the penetration of the carrier wave function into the spacer layer and by the desired device performance. In a specific embodiment, the interface structure is formed in a multi-wafer epitaxial production system including a transfer and load module with a III-V growth chamber attached and an insulator chamber attached.
摘要翻译： 公开了一种绝缘体 - 化合物半导体界面结构，其包括具有半导体材料的隔离层的化合物半导体材料，该间隔层具有比位于化合物半导体材料的表面上的化合物半导体材料的带隙宽的带隙和位于化合物半导体材料的表面上的绝缘层 间隔层。 间隔层的最小和最大厚度由载波函数穿入间隔层和所需器件性能决定。 在具体实施例中，界面结构形成在多晶片外延生产系统中，该系统包括连接有III-V生长室的传输和负载模块，并连接有绝缘体室。
-
公开(公告)号：US5902130A
公开(公告)日：1999-05-11
申请号：US896234
申请日：1997-07-17
IPC分类号： H01L21/265 , H01L21/336 , H01L29/51 , H01L21/28
CPC分类号： H01L21/26553 , H01L29/66522 , H01L29/517 , H01L29/518
摘要： A method of thermal processing a supporting structure comprised of various compound semiconductor layers having a Gd free Ga.sub.2 O.sub.3 surface layer including coating the surface layer with a dielectric or a metallic cap layer or combinations thereof, such that the low D.sub.it Ga.sub.2 O.sub.3 -compound semiconductor structure is conserved during thermal processing, e.g. during activation of ion implants of a self aligned metal-oxide-compound semiconductor gate structure. In a preferred embodiment, the semiconductor structure has a surface of GaAs, the Gd free Ga.sub.2 O.sub.3 layer has a thickness in a range of approximately 1 nm to 20 nm, and the insulating or metallic cap layer has a thickness in a range of approximately 1 nm to 500 nm.
摘要翻译： 一种热处理由具有Gd游离Ga 2 O 3表面层的各种化合物半导体层构成的支撑结构的方法，包括用电介质或金属覆盖层或其组合涂覆表面层，使得低Dit Ga 2 O 3化合物半导体结构被保守 在热处理过程中，例如 在自对准的金属氧化物 - 化合物半导体栅极结构的离子注入的激活期间。 在优选实施例中，半导体结构具有GaAs的表面，Gd自由的Ga 2 O 3层的厚度在约1nm至20nm的范围内，并且绝缘或金属覆盖层的厚度在约1nm的范围内 至500nm。
-
6.发明授权Fabrication method for a gate quality oxide-compound semiconductor structure 失效栅极质量氧化物 - 半导体结构的制造方法
公开(公告)号：US5904553A
公开(公告)日：1999-05-18
申请号：US917119
申请日：1997-08-25
IPC分类号： C23C16/40 , C23C16/44 , C23C16/455 , H01L21/316 , H01L21/3205 , H01L21/4763
CPC分类号： C23C16/45523 , C23C16/407 , C23C16/455 , C23C16/4551 , H01L21/31604
摘要： A method of fabricating a gate quality oxide-compound semiconductor structure includes forming an insulating Ga.sub.2 O.sub.3 layer on the surface of a compound semiconductor wafer structure by a supersonic gas jet containing gallium oxide molecules and oxygen. In a preferred embodiment, a III-V compound semiconductor wafer structure with an atomically ordered and chemically clean semiconductor surface is transferred from a semiconductor growth chamber into an insulator deposition chamber via an ultra high vacuum preparation chamber. Ga.sub.2 O.sub.3 deposition onto the surface of the wafer structure is initiated by a supersonic gas jet pulse and proceeds via optimization of pulse duration, speed of gas jet, mole fraction of gallium oxide molecules and oxygen atoms, and plasma energy.
摘要翻译： 制造栅极质量氧化物半导体结构的方法包括通过含有氧化镓分子和氧的超音速气体射流在化合物半导体晶片结构的表面上形成绝缘Ga 2 O 3层。 在优选实施例中，具有原子级和化学清洁的半导体表面的III-V族化合物半导体晶片结构经由超高真空准备室从半导体生长室转移到绝缘体沉积室中。 通过超音速气体喷射脉冲引发晶片结构表面上的Ga 2 O 3沉积，并且经历脉冲持续时间，气体射流速度，氧化镓分子和氧原子的摩尔分数以及等离子体能量的优化。
-
公开(公告)号：US6030453A
公开(公告)日：2000-02-29
申请号：US812950
申请日：1997-03-04
IPC分类号： H01L21/205 , H01L21/02 , H01L21/31 , H01L21/316 , C30B23/02
CPC分类号： H01L21/31604
摘要： A production process for protecting the surface of compound semiconductor wafers includes providing a multi-wafer epitaxial production system with a transfer and load module, a III-V growth chamber and an insulator chamber. The wafer is placed in the transfer and load module and the pressure is reduced to .ltoreq.10.sup.-10 Torr, after which the wafer is moved to the III-V growth chamber and layers of compound semiconductor material are epitaxially grown on the surface of the wafer. The wafer is then moved through the transfer and load module to the insulator chamber and an insulating cap layer is formed by thermally evaporating gallium oxide molecules from an effusion cell using an evaporation source in an oxide crucible, which oxide crucible does not form an eutectic alloy with the evaporation source
摘要翻译： 用于保护化合物半导体晶片的表面的制造方法包括提供具有传输和负载模块，III-V生长室和绝缘体室的多晶片外延生产系统。 将晶片放置在传送和加载模块中，并将压力降低到10-10托，之后将晶片移动到III-V生长室，并且将化合物半导体材料层外延生长在 晶圆。 然后将晶片通过传输和负载模块移动到绝缘体室，并且通过使用氧化物坩埚中的蒸发源从渗出电池热蒸发氧化镓分子而形成绝缘盖层，该氧化物坩埚不形成共晶合金 与蒸发源
-
8.发明授权Method of fabricating submicron FETs with low temperature group III-V material 失效用低温III-V族材料制造亚微米FET的方法
公开(公告)号：US5937285A
公开(公告)日：1999-08-10
申请号：US863109
申请日：1997-05-23
申请人： Jonathan K. Abrokwah , Ravi Droopad , Corey D. Overgaard , Brian Bowers , Michael P. LaMacchia , Bruce A. Bernhardt
发明人： Jonathan K. Abrokwah , Ravi Droopad , Corey D. Overgaard , Brian Bowers , Michael P. LaMacchia , Bruce A. Bernhardt
IPC分类号： H01L21/20 , H01L21/335 , H01L21/8252 , H01L29/80
CPC分类号： H01L29/802 , H01L21/02395 , H01L21/02463 , H01L21/02505 , H01L21/02546 , H01L21/02631 , H01L21/8252 , H01L29/66462
摘要： A method of fabricating submicron HFETs includes forming a buffered substrate structure with a supporting substrate of GaAs, a portion of low temperature AlGaAs grown on the supporting substrate at a temperature of approximately 300.degree. C., a layer of low temperature GaAs grown on the portion AlGaAs layer at a temperature of 200.degree. C., a layer of low temperature AlGaAs grown on the GaAs layer at a temperature of 400.degree. C., and a buffer layer of undoped GaAs grown on the second AlGaAs layer. Complementary pairs of HFETs can be formed on the buffered substrate structure, since the structure supports the operation of p and n type transistors equally well.
摘要翻译： 制造亚微米HFET的方法包括用GaAs的支撑衬底形成缓冲衬底结构，在约300℃的温度下在支撑衬底上生长一部分低温AlGaAs，在该部分生长的低温GaAs层 AlGaAs层，在400℃的温度下在GaAs层上生长的低温AlGaAs层和在第二AlGaAs层上生长的未掺杂的GaAs的缓冲层。 可以在缓冲衬底结构上形成互补的HFET对，因为该结构同样良好地支持p型和n型晶体管的操作。
-
公开(公告)号：US08847280B2
公开(公告)日：2014-09-30
申请号：US13293910
申请日：2011-11-10
IPC分类号： H01L29/78 , H01L23/31 , H01L29/778 , H01L29/51 , H01L29/207
CPC分类号： H01L29/7783 , H01L23/3192 , H01L29/207 , H01L29/513 , H01L2924/0002 , H01L2924/12044 , H01L2924/13091 , H01L2924/00
摘要： An improved insulated gate field effect device is obtained by providing a substrate desirably comprising a III-V semiconductor, having a further semiconductor layer on the substrate adapted to contain the channel of the device between spaced apart source-drain electrodes formed on the semiconductor layer. A dielectric layer is formed on the semiconductor layer. A sealing layer is formed on the dielectric layer and exposed to an oxygen plasma. A gate electrode is formed on the dielectric layer between the source-drain electrodes. The dielectric layer preferably comprises gallium-oxide and/or gadolinium-gallium oxide, and the oxygen plasma is preferably an inductively coupled plasma. A further sealing layer of, for example, silicon nitride is desirably provided above the sealing layer. Surface states and gate dielectric traps that otherwise adversely affect leakage and channel sheet resistance are much reduced.
摘要翻译： 通过提供期望地包括III-V半导体的衬底来获得改进的绝缘栅场效应器件，所述衬底在衬底上具有另外的半导体层，其适于在形成在半导体层上的间隔开的源 - 漏电极之间容纳器件的沟道。 在半导体层上形成介电层。 在电介质层上形成密封层并暴露于氧等离子体。 在源 - 漏电极之间的电介质层上形成栅电极。 电介质层优选包含氧化镓和/或钆 - 镓氧化物，氧等离子体优选为电感耦合等离子体。 希望在密封层的上方设置另外的例如氮化硅的密封层。 否则对泄漏和通道薄层电阻有不利影响的表面状态和栅极电介质阱将大大减少。
-
公开(公告)号：US08105925B2
公开(公告)日：2012-01-31
申请号：US12182349
申请日：2008-07-30
IPC分类号： H01L21/26
CPC分类号： H01L29/7783 , H01L23/3192 , H01L29/207 , H01L29/513 , H01L2924/0002 , H01L2924/12044 , H01L2924/13091 , H01L2924/00
摘要： An improved insulated gate field effect device (60) is obtained by providing a substrate (20) desirably comprising a III-V semiconductor, having a further semiconductor layer (22) on the substrate (20) adapted to contain the channel (230) of the device (60) between spaced apart source-drain electrodes (421, 422) formed on the semiconductor layer (22). A dielectric layer (24) is formed on the semiconductor layer (22). A sealing layer (28) is formed on the dielectric layer (24) and exposed to an oxygen plasma (36). A gate electrode (482) is formed on the dielectric layer (24) between the source-drain electrodes (421, 422). The dielectric layer (24) preferably comprises gallium-oxide (25) and/or gadolinium-gallium oxide (26, 27), and the oxygen plasma (36) is preferably an inductively coupled plasma. A further sealing layer (44) of, for example, silicon nitride is desirably provided above the sealing layer (28). Surface states and gate dielectric traps that otherwise adversely affect leakage and channel sheet resistance are much reduced.
摘要翻译： 通过提供期望地包括III-V半导体的衬底（20）来获得改进的绝缘栅场效应器件（60），所述衬底（20）在所述衬底（20）上具有另外的半导体层（22），所述半导体层适于容纳所述沟道（230） 所述器件（60）形成在所述半导体层（22）上形成的间隔开的源 - 漏电极（421,422）之间。 在半导体层（22）上形成介电层（24）。 密封层（28）形成在电介质层（24）上并暴露于氧等离子体（36）。 在源漏电极（421,422）之间的电介质层（24）上形成栅电极（482）。 电介质层（24）优选包含氧化镓（25）和/或氧化钆 - 氧化镓（26,27），氧等离子体（36）优选为电感耦合等离子体。 期望地在密封层（28）的上方设置例如氮化硅的另外的密封层（44）。 否则对泄漏和通道薄层电阻有不利影响的表面状态和栅极电介质阱将大大减少。
-
-
-
-
-
-
-
-
-
搜索结果
45 条记录 (耗时 0.019 秒)
