-
公开(公告)号：US08674235B2
公开(公告)日：2014-03-18
申请号：US13153608
申请日：2011-06-06
IPC分类号： H05K3/10
CPC分类号： H05K1/111 , H01L23/49838 , H01L24/16 , H01L2224/131 , H01L2224/16225 , H01L2224/16227 , H01L2224/16237 , H01L2924/12042 , H05K1/112 , H05K3/3436 , H05K2201/09972 , H05K2201/10378 , H01L2924/014 , H01L2924/00
摘要： The present disclosure relates to microelectronic substrates, such as interposers, motherboards, test platforms, and the like, that are fabricated to have overlapping connection zones, such that different microelectronic devices, such as microprocessors, chipsets, graphics processing devices, wireless devices, memory devices, application specific integrated circuits, and the like, may be alternately attached to the microelectronic substrates to form functional microelectronic packages.
摘要翻译： 本公开涉及被制造为具有重叠的连接区域的微电子衬底，例如插入件，母板，测试平台等，使得不同的微电子器件，例如微处理器，芯片组，图形处理器件，无线器件，存储器 设备，专用集成电路等可以交替地附接到微电子基板以形成功能微电子封装。
-
公开(公告)号：US20140133075A1
公开(公告)日：2014-05-15
申请号：US14162002
申请日：2014-01-23
IPC分类号： H05K1/11
CPC分类号： H05K1/111 , H01L23/49838 , H01L24/16 , H01L2224/131 , H01L2224/16225 , H01L2224/16227 , H01L2224/16237 , H01L2924/12042 , H05K1/112 , H05K3/3436 , H05K2201/09972 , H05K2201/10378 , H01L2924/014 , H01L2924/00
摘要： The present disclosure relates to microelectronic substrates, such as interposers, motherboards, test platforms, and the like, that are fabricated to have overlapping connection zones, such that different microelectronic devices, such as microprocessors, chipsets, graphics processing devices, wireless devices, memory devices, application specific integrated circuits, and the like, may be alternately attached to the microelectronic substrates to form functional microelectronic packages.
摘要翻译： 本公开涉及被制造为具有重叠的连接区域的微电子衬底，例如插入件，母板，测试平台等，使得不同的微电子器件，例如微处理器，芯片组，图形处理器件，无线器件，存储器 设备，专用集成电路等可以交替地附接到微电子基板以形成功能微电子封装。
-
公开(公告)号：US20120305303A1
公开(公告)日：2012-12-06
申请号：US13153608
申请日：2011-06-06
CPC分类号： H05K1/111 , H01L23/49838 , H01L24/16 , H01L2224/131 , H01L2224/16225 , H01L2224/16227 , H01L2224/16237 , H01L2924/12042 , H05K1/112 , H05K3/3436 , H05K2201/09972 , H05K2201/10378 , H01L2924/014 , H01L2924/00
摘要： The present disclosure relates to microelectronic substrates, such as interposers, motherboards, test platforms, and the like, that are fabricated to have overlapping connection zones, such that different microelectronic devices, such as microprocessors, chipsets, graphics processing devices, wireless devices, memory devices, application specific integrated circuits, and the like, may be alternately attached to the microelectronic substrates to form functional microelectronic packages.
摘要翻译： 本公开涉及被制造为具有重叠的连接区域的微电子衬底，例如插入件，母板，测试平台等，使得不同的微电子器件，例如微处理器，芯片组，图形处理器件，无线器件，存储器 设备，专用集成电路等可以交替地附接到微电子基板以形成功能微电子封装。
-
公开(公告)号：US20140317343A1
公开(公告)日：2014-10-23
申请号：US14182053
申请日：2014-02-17
CPC分类号： G06F13/1689 , G06F13/1684 , G11C7/1069 , G11C7/1072 , G11C7/1093 , G11C7/22 , G11C2207/2281 , G11C2207/229 , Y02D10/14
摘要： Disclosed embodiments may include a circuit having a plurality of data terminals, no more than two pairs of differential data strobe terminals associated with the plurality of data terminals, and digital logic circuitry. The digital logic circuitry may be coupled to the data terminals and configured to use the no more than two pairs of differential data strobe terminals concurrently with the plurality of data terminals to transfer data. Other embodiments may be disclosed.
-
公开(公告)号：US20140003169A1
公开(公告)日：2014-01-02
申请号：US13535278
申请日：2012-06-27
IPC分类号： G11C7/00
CPC分类号： G06F13/1689 , G06F13/1684 , G11C7/1069 , G11C7/1072 , G11C7/1093 , G11C7/22 , G11C2207/2281 , G11C2207/229 , Y02D10/14
摘要： Disclosed embodiments may include a circuit having a plurality of data terminals, no more than two pairs of differential data strobe terminals associated with the plurality of data terminals, and digital logic circuitry. The digital logic circuitry may be coupled to the data terminals and configured to use the no more than two pairs of differential data strobe terminals concurrently with the plurality of data terminals to transfer data. Other embodiments may be disclosed.
摘要翻译： 公开的实施例可以包括具有多个数据终端的电路，与多个数据终端相关联的不超过两对差分数据选通端子和数字逻辑电路。 数字逻辑电路可以耦合到数据终端，并被配置为与多个数据终端同时使用不超过两对差分数据选通端子来传送数据。 可以公开其他实施例。
-
公开(公告)号：US08683096B2
公开(公告)日：2014-03-25
申请号：US13535278
申请日：2012-06-27
IPC分类号： G06F3/00
CPC分类号： G06F13/1689 , G06F13/1684 , G11C7/1069 , G11C7/1072 , G11C7/1093 , G11C7/22 , G11C2207/2281 , G11C2207/229 , Y02D10/14
摘要： Disclosed embodiments may include a circuit having a plurality of data terminals, no more than two pairs of differential data strobe terminals associated with the plurality of data terminals, and digital logic circuitry. The digital logic circuitry may be coupled to the data terminals and configured to use the no more than two pairs of differential data strobe terminals concurrently with the plurality of data terminals to transfer data. Other embodiments may be disclosed.
摘要翻译： 公开的实施例可以包括具有多个数据终端的电路，与多个数据终端相关联的不超过两对差分数据选通端子和数字逻辑电路。 数字逻辑电路可以耦合到数据终端，并被配置为与多个数据终端同时使用不超过两对差分数据选通端子来传送数据。 可以公开其他实施例。
-
-
-
-
-
搜索结果
6 条记录 (耗时 0.028 秒)
