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    Sidewall coverage for copper damascene filling
    1.
    发明授权
    Sidewall coverage for copper damascene filling 有权
    铜镶嵌填料的侧壁覆盖

    公开(公告)号：US07282450B2

    公开(公告)日：2007-10-16

    申请号：US10733722

    申请日：2003-12-11

    申请人： Shau-Lin Shue ,  Mei-Yun Wang ,  Chen-Hua Yu

    发明人： Shau-Lin Shue ,  Mei-Yun Wang ,  Chen-Hua Yu

    IPC分类号： H01L21/44

    CPC分类号： H01L21/76843 ,  H01L21/2855 ,  H01L21/76862 ,  H01L21/76865 ,  H01L21/76873 ,  H01L21/76874 ,  H01L2221/1089

    摘要： A general process is described for filling a hole or trench at the surface of an integrated circuit without trapping voids within the filler material. A particular application is the filling of a trench with copper in order to form damascene wiring. First, a seed layer is deposited in the hole or trench by means of PVD. This is then followed by a sputter etching step which removes any overhang of this seed layer at the mouth of the trench or hole. A number of process variations are described including double etch/deposit steps, varying pressure and voltage in the same chamber to allow sputter etching and deposition to take place without breaking vacuum, and reduction of contact resistance between wiring levels by reducing via depth.

    摘要翻译： 描述了在集成电路的表面处填充孔或沟槽而不在填充材料内捕获空隙的一般方法。 具体应用是用铜填充沟槽以形成镶嵌线。 首先，通过PVD将种子层沉积在孔或沟槽中。 然后进行溅射蚀刻步骤，其移除沟槽或孔口处的该种子层的任何突出端。 描述了许多工艺变化，包括双重蚀刻/沉积步骤，在相同的室中改变压力和电压，以允许在不破坏真空的情况下进行溅射蚀刻和沉积，并且通过减小通孔深度来降低布线水平之间的接触电阻。

    Method of passivating a metal line prior to deposition of a fluorinated silica glass layer
    2.
    发明授权
    Method of passivating a metal line prior to deposition of a fluorinated silica glass layer 有权
    在沉积氟化石英玻璃层之前钝化金属线的方法

    公开(公告)号：US06242338B1

    公开(公告)日：2001-06-05

    申请号：US09422175

    申请日：1999-10-22

    申请人： Chung-Shi Liu ,  Shau-Lin Shue ,  Yao-yi Cheng ,  Chen-Hua Yu ,  Mei-Yun Wang

    发明人： Chung-Shi Liu ,  Shau-Lin Shue ,  Yao-yi Cheng ,  Chen-Hua Yu ,  Mei-Yun Wang

    IPC分类号： H01L214763

    CPC分类号： H01L21/02131 ,  H01L21/02274 ,  H01L21/02304 ,  H01L21/31629 ,  H01L21/321 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76888

    摘要： A process of forming a thin, protective insulator layer, on the sides of metal interconnect structures, prior to the deposition of a halogen containing, low k dielectric layer, has been developed. The process features the growth of a thin metal nitride, or thin metal oxide layer, on the exposed sides of the metal interconnect structures, via a plasma treatment, performed in either a nitrogen containing, or in a water containing, ambient. The thin layer protects the metal interconnect structure from the corrosive, as well as delamination effects, created by the halogen, or halogen products, contained in overlying low k dielectric layers, such as fluorinated silica glass.

    摘要翻译： 已经开发了在沉积含卤素的低k电介质层之前在金属互连结构的侧面上形成薄的保护性绝缘体层的工艺。 该方法的特征在于金属互连结构的暴露侧上通过等离子体处理在含氮或含水环境中进行的金属氮化物或薄金属氧化物层的生长。 薄层保护金属互连结构免受由覆盖在低k电介质层（例如氟化石英玻璃）中的卤素或卤素产物产生的腐蚀性以及分层影响。

    Sidewall coverage for copper damascene filling
    3.
    发明授权
    Sidewall coverage for copper damascene filling 有权
    铜镶嵌填料的侧壁覆盖

    公开(公告)号：US07514348B2

    公开(公告)日：2009-04-07

    申请号：US11860639

    申请日：2007-09-25

    申请人： Shau-Lin Shue ,  Mei-Yun Wang ,  Chen-Hua Yu

    发明人： Shau-Lin Shue ,  Mei-Yun Wang ,  Chen-Hua Yu

    IPC分类号： H01L21/302

    CPC分类号： H01L21/76843 ,  H01L21/2855 ,  H01L21/76862 ,  H01L21/76865 ,  H01L21/76873 ,  H01L21/76874 ,  H01L2221/1089

    摘要： A general process is described for filling a hole or trench at the surface of an integrated circuit without trapping voids within the filler material. A particular application is the filling of a trench with copper in order to form damascene wiring. First, a seed layer is deposited in the hole or trench by means of PVD. This is then followed by a sputter etching step which removes any overhang of this seed layer at the mouth of the trench or hole. A number of process variations are described including double etch/deposit steps, varying pressure and voltage in the same chamber to allow sputter etching and deposition to take place without breaking vacuum, and reduction of contact resistance between wiring levels by reducing via depth.

    摘要翻译： 描述了在集成电路的表面处填充孔或沟槽而不在填充材料内捕获空隙的一般方法。 具体应用是用铜填充沟槽以形成镶嵌线。 首先，通过PVD将种子层沉积在孔或沟槽中。 然后进行溅射蚀刻步骤，其移除沟槽或孔口处的该种子层的任何突出端。 描述了许多工艺变化，包括双重蚀刻/沉积步骤，在相同的室中改变压力和电压，以允许在不破坏真空的情况下进行溅射蚀刻和沉积，并且通过减小通孔深度来降低布线水平之间的接触电阻。

    Sidewall coverage for copper damascene filling
    4.
    发明授权
    Sidewall coverage for copper damascene filling 有权

    公开(公告)号：US06686280B1

    公开(公告)日：2004-02-03

    申请号：US09989802

    申请日：2001-11-20

    申请人： Shau-Lin Shue ,  Mei-Yun Wang ,  Chen-Hua Yu

    发明人： Shau-Lin Shue ,  Mei-Yun Wang ,  Chen-Hua Yu

    IPC分类号： H01L2100

    CPC分类号： H01L21/76843 ,  H01L21/2855 ,  H01L21/76862 ,  H01L21/76865 ,  H01L21/76873 ,  H01L21/76874 ,  H01L2221/1089

    摘要： A general process is described for filling a hole or trench at the surface of an integrated circuit without trapping voids within the filler material. A particular application is the filling of a trench with copper in order to form damascene wiring. First, a seed layer is deposited in the hole or trench by means of PVD. This is then followed by a sputter etching step which removes any overhang of this seed layer at the mouth of the trench or hole. A number of process variations are described including double etch/deposit steps, varying pressure and voltage in the same chamber to allow sputter etching and deposition to take place without breaking vacuum, and reduction of contact resistance between wiring levels by reducing via depth.

    Sidewall Coverage For Copper Damascene Filling
    5.
    发明申请
    Sidewall Coverage For Copper Damascene Filling 有权
    铜镶嵌填料的侧壁覆盖

    公开(公告)号：US20080009133A1

    公开(公告)日：2008-01-10

    申请号：US11860639

    申请日：2007-09-25

    申请人： Shau-Lin Shue ,  Mei-Yun Wang ,  Chen-Hua Yu

    发明人： Shau-Lin Shue ,  Mei-Yun Wang ,  Chen-Hua Yu

    IPC分类号： H01L21/4763

    CPC分类号： H01L21/76843 ,  H01L21/2855 ,  H01L21/76862 ,  H01L21/76865 ,  H01L21/76873 ,  H01L21/76874 ,  H01L2221/1089

    摘要： A general process is described for filling a hole or trench at the surface of an integrated circuit without trapping voids within the filler material. A particular application is the filling of a trench with copper in order to form damascene wiring. First, a seed layer is deposited in the hole or trench by means of PVD. This is then followed by a sputter etching step which removes any overhang of this seed layer at the mouth of the trench or hole. A number of process variations are described including double etch/deposit steps, varying pressure and voltage in the same chamber to allow sputter etching and deposition to take place without breaking vacuum, and reduction of contact resistance between wiring levels by reducing via depth.

    摘要翻译： 描述了在集成电路的表面处填充孔或沟槽而不在填充材料内捕获空隙的一般方法。 具体应用是用铜填充沟槽以形成镶嵌线。 首先，通过PVD将种子层沉积在孔或沟槽中。 然后进行溅射蚀刻步骤，其移除沟槽或孔口处的该种子层的任何突出端。 描述了许多工艺变化，包括双重蚀刻/沉积步骤，在相同的室中改变压力和电压，以允许在不破坏真空的情况下进行溅射蚀刻和沉积，并且通过减小通孔深度来降低布线水平之间的接触电阻。

    Key-hole reduction during tungsten plug formation
    6.
    发明授权
    Key-hole reduction during tungsten plug formation 有权
    钨丝塞形成期间的关键孔减少

    公开(公告)号：US6096651A

    公开(公告)日：2000-08-01

    申请号：US228126

    申请日：1999-01-11

    申请人： Mei-Yun Wang ,  Chen-Hua Yu ,  Shau-Lin Shue

    发明人： Mei-Yun Wang ,  Chen-Hua Yu ,  Shau-Lin Shue

    IPC分类号： H01L21/768 ,  H01L21/302

    CPC分类号： H01L21/76865 ,  H01L21/76804 ,  H01L21/76843 ,  H01L21/76862

    摘要： The problem of key-hole formation during the filling of small diameter via holes has been overcome by means of soft sputtering in argon after the barrier layer is in place. This sputtering step may be used twice--once to widen the mouth of a newly formed via hole, and a second time after the barrier layer is in place, thereby widening the mouth further (as well as removing oxide from the surface of the barrier layer). In an alternate optional embodiment, widening of the via hole mouth may be limited to a single sputtering step after the barrier layer has been laid down. In either case, this is followed by filling of the via hole which occurs without any key-hole formation.

    摘要翻译： 通过在阻挡层就位之后的氩气中的软溅射，克服了在小直径通孔填充期间形成孔洞的问题。 该溅射步骤可以使用两次一次来加宽新形成的通孔的口，并且在阻挡层就位之后的第二次，从而进一步扩大口（以及从阻挡层的表面去除氧化物） ）。 在替代的可选实施例中，通孔口的加宽可以在阻挡层被铺设之后被限制到单个溅射步骤。 在任一种情况下，随后填充通孔而没有任何键孔形成。

    Copper interconnect structure and method for forming the same
    7.
    发明授权
    Copper interconnect structure and method for forming the same 有权
    铜互连结构及其形成方法

    公开(公告)号：US08941239B2

    公开(公告)日：2015-01-27

    申请号：US13586676

    申请日：2012-08-15

    申请人： Chen-Hua Yu ,  Shau-Lin Shue ,  Hsiang-Huan Lee ,  Ching-Fu Yeh

    发明人： Chen-Hua Yu ,  Shau-Lin Shue ,  Hsiang-Huan Lee ,  Ching-Fu Yeh

    IPC分类号： H01L23/48 ,  H01L21/14

    CPC分类号： H01L21/76871 ,  H01L21/76846 ,  H01L2221/1089

    摘要： A copper interconnect structure in a semiconductor device including an opening formed in a dielectric layer of the semiconductor device, the opening having sidewalls and a bottom. A first barrier layer is conformally deposited on the sidewalls and the bottom of the opening. A first seed layer is conformally deposited on the first barrier layer. A second barrier layer is conformally deposited on the first seed layer. A second seed layer is conformally deposited on the second barrier layer and a conductive plug is deposited in the opening of the dielectric layer.

    摘要翻译： 一种半导体器件中的铜互连结构，包括形成在半导体器件的电介质层中的开口，该开口具有侧壁和底部。 第一阻挡层保形地沉积在开口的侧壁和底部上。 第一种子层共形沉积在第一阻挡层上。 第二阻挡层被共形沉积在第一籽晶层上。 第二种子层被共形沉积在第二阻挡层上，并且导电塞被沉积在电介质层的开口中。

    Low resistance high reliability contact via and metal line structure for semiconductor device
    9.
    发明授权
    Low resistance high reliability contact via and metal line structure for semiconductor device 有权
    低电阻高可靠性接触通孔和半导体器件的金属线结构

    公开(公告)号：US08106512B2

    公开(公告)日：2012-01-31

    申请号：US12845852

    申请日：2010-07-29

    申请人： Hsiang-Huan Lee ,  Ming Han Lee ,  Ming-Shih Yeh ,  Chen-Hua Yu ,  Shau-Lin Shue

    发明人： Hsiang-Huan Lee ,  Ming Han Lee ,  Ming-Shih Yeh ,  Chen-Hua Yu ,  Shau-Lin Shue

    IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40

    CPC分类号： H01L23/53238 ,  H01L21/28562 ,  H01L21/76846 ,  H01L21/76867 ,  H01L21/76873 ,  H01L21/76883 ,  H01L23/485 ,  H01L2924/0002 ,  H01L2924/00

    摘要： The structures and methods described above provide mechanisms to improve interconnect reliability and resistivity. The interconnect reliability and resistivity are improved by using a composite barrier layer, which provides good step coverage, good copper diffusion barrier, and good adhesion with adjacent layers. The composite barrier layer includes an ALD barrier layer to provide good step coverage. The composite barrier layer also includes a barrier-adhesion-enhancing film, which contains at least an element or compound that contains Mn, Cr, V, Ti, or Nb to improve adhesion. The composite barrier layer may also include a Ta or Ti layer between the ALD barrier layer and the barrier-adhesion-enhancing layer.

    摘要翻译： 上述结构和方法提供了提高互连可靠性和电阻率的机制。 通过使用复合阻挡层来提高互连的可靠性和电阻率，该复合阻挡层提供良好的台阶覆盖率，良好的铜扩散阻挡层和与相邻层的良好粘附性。 复合阻挡层包括ALD阻挡层以提供良好的阶梯覆盖。 复合阻挡层还包括至少包含含有Mn，Cr，V，Ti或Nb的元素或化合物以提高粘合性的阻隔增粘膜。 复合阻挡层还可以包括在ALD阻挡层和阻挡增粘层之间的Ta或Ti层。