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11 条记录 (耗时 0.04 秒)

    Integrated circuit having air gaps between dielectric and conducting lines
    1.
    发明授权
    Integrated circuit having air gaps between dielectric and conducting lines 有权
    在电介质和导线之间具有气隙的集成电路

    公开(公告)号：US06342722B1

    公开(公告)日：2002-01-29

    申请号：US09369082

    申请日：1999-08-05

    申请人： Michael Armacost ,  Peter D. Hoh ,  David V. Horak ,  Richard S. Wise

    发明人： Michael Armacost ,  Peter D. Hoh ,  David V. Horak ,  Richard S. Wise

    IPC分类号： H01L2900

    CPC分类号： H01L23/5222 ,  H01L2924/0002 ,  H01L2924/00

    摘要： An integrated circuit and method of making the integrated circuit. Air gaps are formed between surfaces of current-conducting lines that face one another and dielectric material disposed between these surfaces of the current-conducting lines. A liner material is applied to these surfaces of the current-conducting lines and, after the dielectric material is introduced between the current-conducting lines, the liner material is removed, for example by etching, leaving air gaps between the current-conducting lines and the dielectric material. These air gaps eliminate or greatly reduce the effect of capacitive currents across the dielectric material between the current-conducting lines.

    摘要翻译： 集成电路和集成电路的制造方法。 导电线的表面之间形成气隙，并且设置在导电线的这些表面之间的电介质材料。 将衬垫材料施加到导电线的这些表面，并且在电介质材料被引入导电线之后，衬里材料例如通过蚀刻被去除，在导电线之间留下空气间隙 介电材料。 这些气隙消除或大大降低了导电线之间的电介质材料之间的电容电流的影响。

    High-density plasma, organic anti-reflective coating etch system compatible with sensitive photoresist materials
    2.
    发明授权
    High-density plasma, organic anti-reflective coating etch system compatible with sensitive photoresist materials 失效
    高密度等离子体，有机抗反射涂层蚀刻系统兼容敏感光刻胶材料

    公开(公告)号：US06228279B1

    公开(公告)日：2001-05-08

    申请号：US09156065

    申请日：1998-09-17

    申请人： Michael Armacost ,  Peter Hoh ,  Richard S. Wise ,  Wendy Yan

    发明人： Michael Armacost ,  Peter Hoh ,  Richard S. Wise ,  Wendy Yan

    IPC分类号： H01L213065

    CPC分类号： H01L21/31138

    摘要： By providing a photoresist material with a protective polymer layer during the etching of an organic anti-reflective coating, undue damage to the photoresist material can be avoided during opening of the anti-reflective coating without the need for an oxidant. The preferred polymer chemistry system for producing such a result includes a fluorohydrocarbon-containing polymer mixture with a strong source of CF3, preferably C2F6. The etchant also includes a source of hydrogen selected from CH3F, C2HF5, or CH2F2, and a diluent selected from Ar, He or N2.

    摘要翻译： 在蚀刻有机抗反射涂层期间通过提供具有保护性聚合物层的光致抗蚀剂材料，可以在打开抗反射涂层期间避免对光致抗蚀剂材料的过度损坏而不需要氧化剂。 用于产生这种结果的优选聚合物化学体系包括具有强的CF 3源，优选C 2 F 6的含氟代烃的聚合物混合物。 蚀刻剂还包括选自CH 3 F，C 2 H 5或CH 2 F 2的氢源和选自Ar，He或N 2的稀释剂。

    ETCH DEPTH CONTROL FOR DUAL DAMASCENE FABRICATION PROCESS
    3.
    发明申请
    ETCH DEPTH CONTROL FOR DUAL DAMASCENE FABRICATION PROCESS 失效
    用于双重生物制剂工艺的ETCH深度控制

    公开(公告)号：US20080102638A1

    公开(公告)日：2008-05-01

    申请号：US11877964

    申请日：2007-10-24

    申请人： MEHUL NAIK ,  Suketu Parikh ,  Michael Armacost

    发明人： MEHUL NAIK ,  Suketu Parikh ,  Michael Armacost

    IPC分类号： H01L21/311

    CPC分类号： H01L21/31116 ,  H01J37/32091 ,  H01J37/3266 ,  H01J2237/3347 ,  H01L21/76807 ,  H01L21/76808 ,  H01L22/26

    摘要： The etch depth during trench over via etch of a dual damascene structure in a dielectric film stack is controlled to be the same over the dense area and the open area of a substrate and solve micro-loading problems. The trench etch process is adapted to include a forward micro-loading etching process and a reverse micro-loading etching process using two etch chemistries together with the inclusion of a dopant material layer or an organic fill material layer during the deposition of the dielectric film stack. In one embodiment, etching of trenches over vias is switched from forward micro-loading to reverse micro-loading once etching of the dielectric film stack is reached at a predetermined location of a dopant material layer. In another embodiment, etching of an organic trench filling material layer is performed in a reverse micro-loading process followed by etching the dielectric film stack in a forward micro-loading process.

    摘要翻译： 电介质膜堆叠中的双镶嵌结构的沟槽过孔蚀刻中的蚀刻深度被控制为在基底的致密区域和开放区域上相同，并且解决微加载问题。 沟槽蚀刻工艺适于包括使用两个蚀刻化学物质的正向微加载蚀刻工艺和反向微加载蚀刻工艺，以及在沉积介电膜堆叠期间包含掺杂剂材料层或有机填充材料层 。 在一个实施例中，一旦在掺杂剂材料层的预定位置处达到电介质膜堆叠的蚀刻，则在通孔上的沟槽的蚀刻从正向微负载切换到反向微负载。 在另一个实施例中，有机沟槽填充材料层的蚀刻在反向微加载过程中进行，然后在正向微加载过程中蚀刻介电膜堆叠。

    Dielectric materials to prevent photoresist poisoning
    4.
    发明申请
    Dielectric materials to prevent photoresist poisoning 失效
    介电材料防止光致抗蚀剂中毒

    公开(公告)号：US20050014361A1

    公开(公告)日：2005-01-20

    申请号：US10847891

    申请日：2004-05-18

    申请人： Son Nguyen ,  Michael Armacost ,  Mehul Naik ,  Girish Dixit ,  Ellie Yieh

    发明人： Son Nguyen ,  Michael Armacost ,  Mehul Naik ,  Girish Dixit ,  Ellie Yieh

    IPC分类号： H01L21/4763 ,  H01L21/768

    CPC分类号： H01L21/76808

    摘要： Methods are provided for depositing a dielectric material for use as an anti-reflective coating and sacrificial dielectric material in damascene formation. In one aspect, a process is provided for processing a substrate including depositing an acidic dielectric layer on the substrate by reacting an oxygen-containing organosilicon compound and an acidic compound, depositing a photoresist material on the acidic dielectric layer, and patterning the photoresist layer. The acidic dielectric layer may be used as a sacrificial layer in forming a feature definition by etching a partial feature definition, depositing the acidic dielectric material, etching the remainder of the feature definition, and then removing the acidic dielectric material to form a feature definition.

    摘要翻译： 提供了用于沉积电介质材料的方法，用作防蚀涂层和牺牲电介质材料在镶嵌形成中。 在一个方面，提供了一种处理衬底的方法，包括通过使含氧有机硅化合物和酸性化合物反应，在酸性电介质层上沉积光致抗蚀剂材料，并使光致抗蚀剂层图形化，在衬底上沉积酸性介电层。 通过蚀刻部分特征定义，沉积酸性电介质材料，蚀刻特征定义的其余部分，然后除去酸性介电材料以形成特征定义，可以将酸性介电层用作形成特征定义的牺牲层。

    METHODS FOR SELECTIVELY ETCHING A BARRIER LAYER IN DUAL DAMASCENE APPLICATIONS
    7.
    发明申请
    METHODS FOR SELECTIVELY ETCHING A BARRIER LAYER IN DUAL DAMASCENE APPLICATIONS 审中-公开
    在双重大气应用中选择障碍层的方法

    公开(公告)号：US20090117745A1

    公开(公告)日：2009-05-07

    申请号：US11934285

    申请日：2007-11-02

    申请人： SIYI LI ,  Michael Armacost

    发明人： SIYI LI ,  Michael Armacost

    IPC分类号： H01L21/311

    CPC分类号： H01L21/31116 ,  H01L21/76807 ,  H01L21/76834

    摘要： Methods for etching a dielectric barrier layer with high selectivity to a dielectric bulk insulating layer and/or a hardmask layer in a dual damascene structure are provided. In one embodiment, the method includes providing a substrate having a portion of a dielectric barrier layer exposed through a dielectric bulk insulating layer in an etch reactor, flowing a gas mixture containing SiF4 gas into the reactor, and etching the exposed portion of the dielectric barrier layer selectively to the dielectric bulk insulating layer using a plasma formed from the gas mixture.

    摘要翻译： 提供了在双镶嵌结构中蚀刻具有高介电体绝缘层和/或硬掩模层的高选择性的介电阻挡层的方法。 在一个实施例中，该方法包括提供衬底，该衬底具有通过蚀刻反应器中的绝缘体绝缘层暴露的介电阻挡层的一部分，将含有SiF 4气体的气体混合物流入反应器中，以及蚀刻介电阻挡层的暴露部分 使用由气体混合物形成的等离子体选择性地层压到介电体绝缘层。

    Method of eliminating a critical mask using a blockout mask and a resulting semiconductor structure
    8.
    发明授权
    Method of eliminating a critical mask using a blockout mask and a resulting semiconductor structure 失效
    使用阻挡掩模和所得半导体结构消除临界掩模的方法

    公开(公告)号：US06232222B1

    公开(公告)日：2001-05-15

    申请号：US09395418

    申请日：1999-09-14

    申请人： Michael Armacost ,  Richard A. Conti ,  Jeffrey P. Gambino ,  Jeremy K. Stephens

    发明人： Michael Armacost ,  Richard A. Conti ,  Jeffrey P. Gambino ,  Jeremy K. Stephens

    IPC分类号： H01L214763

    CPC分类号： H01L21/76897 ,  H01L21/31144 ,  H01L27/10873 ,  H01L27/10894

    摘要： A method of forming a semiconductor structure may include forming a semiconductor substrate having an array region and a support region, forming a semiconductor substrate and a gate stack over the support region of the substrate and applying a critical mask over the support region and the array region. The critical mask may have a first opening at an area corresponding to the array region and a second opening at an area corresponding to the support region. Contact holes may be formed in a glass layer at areas corresponding to the first and second opening. After removing the critical mask, a first blockout mask may be applied over the array region and a first conductive type dopant may be added to exposed polysilicon corresponding to openings of the blockout mask or gate contacts may be formed.

    摘要翻译： 形成半导体结构的方法可以包括形成具有阵列区域和支撑区域的半导体衬底，在衬底的支撑区域上形成半导体衬底和栅叠层，并在衬底区域和阵列区域上施加临界掩模 。 临界掩模可以在对应于阵列区域的区域处具有第一开口，并且在对应于支撑区域的区域处具有第二开口。 可以在对应于第一和第二开口的区域的玻璃层中形成接触孔。 在去除临界掩模之后，可以在阵列区域上施加第一堵塞掩模，并且可以形成第一导电型掺杂剂，以对应于封闭掩模的开口或栅极触点形成对应于暴露的多晶硅。