公开(公告)号：US08058732B2

公开(公告)日：2011-11-15

申请号：US12275086

申请日：2008-11-20

申请人： Michael D. Gruenhagen ,  Suku Kim ,  James J. Murphy ,  Ihsiu Ho ,  Eddy Tjhia ,  Chung-Lin Wu ,  Mark Larsen ,  Rohit Dikshit

发明人： Michael D. Gruenhagen ,  Suku Kim ,  James J. Murphy ,  Ihsiu Ho ,  Eddy Tjhia ,  Chung-Lin Wu ,  Mark Larsen ,  Rohit Dikshit

IPC分类号： H01L23/48

CPC分类号： H01L29/7802 ,  H01L23/3114 ,  H01L23/36 ,  H01L23/482 ,  H01L24/16 ,  H01L24/19 ,  H01L24/31 ,  H01L29/0657 ,  H01L2224/04105 ,  H01L2224/20 ,  H01L2224/73253 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/1461 ,  H01L2924/351 ,  H01L2924/00

摘要： Disclosed are semiconductor die structures that enable a die having a vertical power device to be packaged in a wafer-level chip scale package where the current-conducting terminals are present at one surface of the die, and where the device has very low on-state resistance. In an exemplary embodiment, a trench and an aperture are formed in a backside of a die, with the aperture contacting a conductive region at the top surface of the die. A conductive layer and/or a conductive body may be disposed on the trench and aperture to electrically couple the backside current-conducting electrode of the device to the conductive region. Also disclosed are packages and systems using a die with a die structure according to the invention, and methods of making dice with a die structure according to the invention.

摘要翻译： 公开了半导体管芯结构，其使具有垂直功率器件的管芯封装在晶片级芯片级封装中，其中导电端子存在于管芯的一个表面处，并且器件具有非常低的导通状态 抵抗性。 在示例性实施例中，沟槽和孔形成在管芯的背面，孔与导管的顶表面处的导电区接触。 可以在沟槽和孔上设置导电层和/或导体，以将器件的背面导电电极电耦合到导电区域。 还公开了使用根据本发明的具有模具结构的模具的封装和系统，以及根据本发明的具有模具结构的模具的方法。

公开(公告)号：US20100123225A1

公开(公告)日：2010-05-20

申请号：US12275086

申请日：2008-11-20

申请人： Michael D. Gruenhagen ,  Suku Kim ,  James J. Murphy ,  Ihsiu Ho ,  Eddy Tjhia ,  Chung-Lin Wu ,  Mark Larsen ,  Rohit Dikshit

发明人： Michael D. Gruenhagen ,  Suku Kim ,  James J. Murphy ,  Ihsiu Ho ,  Eddy Tjhia ,  Chung-Lin Wu ,  Mark Larsen ,  Rohit Dikshit

IPC分类号： H01L23/495 ,  H01L21/60

CPC分类号： H01L29/7802 ,  H01L23/3114 ,  H01L23/36 ,  H01L23/482 ,  H01L24/16 ,  H01L24/19 ,  H01L24/31 ,  H01L29/0657 ,  H01L2224/04105 ,  H01L2224/20 ,  H01L2224/73253 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/1461 ,  H01L2924/351 ,  H01L2924/00

摘要： Disclosed are semiconductor die structures that enable a die having a vertical power device to be packaged in a wafer-level chip scale package where the current-conducting terminals are present at one surface of the die, and where the device has very low on-state resistance. In an exemplary embodiment, a trench and an aperture are formed in a backside of a die, with the aperture contacting a conductive region at the top surface of the die. A conductive layer and/or a conductive body may be disposed on the trench and aperture to electrically couple the backside current-conducting electrode of the device to the conductive region. Also disclosed are packages and systems using a die with a die structure according to the invention, and methods of making dice with a die structure according to the invention.

摘要翻译： 公开了半导体管芯结构，其使具有垂直功率器件的管芯封装在晶片级芯片级封装中，其中导电端子存在于管芯的一个表面处，并且器件具有非常低的导通状态 抵抗性。 在示例性实施例中，沟槽和孔形成在管芯的背面，孔与导管的顶表面处的导电区接触。 可以在沟槽和孔上设置导电层和/或导体，以将器件的背面导电电极电耦合到导电区域。 还公开了使用根据本发明的具有模具结构的模具的封装和系统，以及根据本发明的具有模具结构的模具的方法。

公开(公告)号：US08502313B2

公开(公告)日：2013-08-06

申请号：US13091578

申请日：2011-04-21

申请人： Rohit Dikshit ,  Mark L. Rinehimer ,  Michael D. Gruenhagen ,  Joseph A. Yedinak ,  Tracie Petersen ,  Ritu Sodhi ,  Dan Kinzer ,  Christopher L. Rexer ,  Fred C. Session

发明人： Rohit Dikshit ,  Mark L. Rinehimer ,  Michael D. Gruenhagen ,  Joseph A. Yedinak ,  Tracie Petersen ,  Ritu Sodhi ,  Dan Kinzer ,  Christopher L. Rexer ,  Fred C. Session

IPC分类号： H01L29/76

CPC分类号： H01L29/7813 ,  H01L24/05 ,  H01L29/41775 ,  H01L29/42372 ,  H01L29/7397 ,  H01L29/7455 ,  H01L29/7811 ,  H01L2224/04034 ,  H01L2224/04042 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2924/01327 ,  H01L2924/1301 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/01079 ,  H01L2924/00014 ,  H01L2924/01028 ,  H01L2924/01047 ,  H01L2924/01023 ,  H01L2924/01014 ,  H01L2924/01029 ,  H01L2924/00

摘要： This document discusses, among other things, a semiconductor device including a first metal layer coupled to a source region and a second metal layer coupled to a gate structure, wherein at least a portion of the first and second metal layers overlap vertically.

摘要翻译： 本文件尤其涉及包括耦合到源区的第一金属层和耦合到栅极结构的第二金属层的半导体器件，其中第一和第二金属层的至少一部分垂直重叠。

公开(公告)号：US20110062564A1

公开(公告)日：2011-03-17

申请号：US12561988

申请日：2009-09-17

申请人： Michael D. Gruenhagen ,  Rohit Dikshit

发明人： Michael D. Gruenhagen ,  Rohit Dikshit

IPC分类号： H01L23/495 ,  H01L21/50

CPC分类号： H01L29/0657 ,  H01L21/30608 ,  H01L21/78 ,  H01L23/49506 ,  H01L24/48 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/10253 ,  H01L2924/12032 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： Methods for singulating a semiconductor wafer into a plurality of individual dies that contain lateral edges or sidewalls and the semiconductor dies formed from these methods are described. The dies are formed from methods that use a front to back photolithography alignment process to form a photo-resist mask and an anisoptropic wet etch in an HNA and/or a TMAH solution on the backside of the wafer through the photoresist mask to form sloped sidewalls and/or textures. The conditions of the TMAH etching process can be controlled to form any desired combination of rough or smooth sidewalls. Thus, the dies formed have a Si front side with an area larger than the Si backside area and sidewalls or lateral edges that are not perpendicular to the front or back surface of the die. Other embodiments are also described.

摘要翻译： 描述了将半导体晶片分离成包含侧边缘或侧壁的多个单独晶粒以及由这些方法形成的半导体管芯的方法。 模具由使用从前到后的光刻对准工艺以通过光致抗蚀剂掩模在晶片背面上的HNA和/或TMAH溶液中形成光刻胶掩模和不对称湿蚀刻的方法形成，以形成倾斜的侧壁 和/或纹理。 可以控制TMAH蚀刻工艺的条件以形成粗糙或平滑侧壁的任何期望的组合。 因此，形成的模具具有比Si背面区域大的Si前侧和不垂直于模具的前表面或后表面的侧壁或侧边缘。 还描述了其它实施例。

公开(公告)号：US20120267714A1

公开(公告)日：2012-10-25

申请号：US13091578

申请日：2011-04-21

申请人： Rohit Dikshit ,  Mark L. Rinehimer ,  Michael D. Gruenhagen ,  Joseph A. Yedinak ,  Tracie Petersen ,  Ritu Sodhi ,  Dan Kinzer ,  Christopher L. Rexer ,  Fred Session

发明人： Rohit Dikshit ,  Mark L. Rinehimer ,  Michael D. Gruenhagen ,  Joseph A. Yedinak ,  Tracie Petersen ,  Ritu Sodhi ,  Dan Kinzer ,  Christopher L. Rexer ,  Fred Session

IPC分类号： H01L29/78 ,  H01L21/28

CPC分类号： H01L29/7813 ,  H01L24/05 ,  H01L29/41775 ,  H01L29/42372 ,  H01L29/7397 ,  H01L29/7455 ,  H01L29/7811 ,  H01L2224/04034 ,  H01L2224/04042 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2924/01327 ,  H01L2924/1301 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/01079 ,  H01L2924/00014 ,  H01L2924/01028 ,  H01L2924/01047 ,  H01L2924/01023 ,  H01L2924/01014 ,  H01L2924/01029 ,  H01L2924/00

摘要： This document discusses, among other things, a semiconductor device including a first metal layer coupled to a source region and a second metal layer coupled to a gate structure, wherein at least a portion of the first and second metal layers overlap vertically.

摘要翻译： 本文件尤其涉及包括耦合到源区的第一金属层和耦合到栅极结构的第二金属层的半导体器件，其中第一和第二金属层的至少一部分垂直重叠。

公开(公告)号：US08072044B2

公开(公告)日：2011-12-06

申请号：US12561988

申请日：2009-09-17

申请人： Michael D. Gruenhagen ,  Rohit Dikshit

发明人： Michael D. Gruenhagen ,  Rohit Dikshit

IPC分类号： H01L29/06

CPC分类号： H01L29/0657 ,  H01L21/30608 ,  H01L21/78 ,  H01L23/49506 ,  H01L24/48 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/10253 ,  H01L2924/12032 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： Methods for singulating a semiconductor wafer into a plurality of individual dies that contain lateral edges or sidewalls and the semiconductor dies formed from these methods are described. The dies are formed from methods that use a front to back photolithography alignment process to form a photo-resist mask and an anisoptropic wet etch in an HNA and/or a TMAH solution on the backside of the wafer through the photoresist mask to form sloped sidewalls and/or textures. The conditions of the TMAH etching process can be controlled to form any desired combination of rough or smooth sidewalls. Thus, the dies formed have a Si front side with an area larger than the Si backside area and sidewalls or lateral edges that are not perpendicular to the front or back surface of the die. Other embodiments are also described.

摘要翻译： 描述了将半导体晶片分离成包含侧边缘或侧壁的多个单独晶粒以及由这些方法形成的半导体管芯的方法。 模具由使用从前到后的光刻对准工艺以通过光致抗蚀剂掩模在晶片背面上的HNA和/或TMAH溶液中形成光刻胶掩模和不对称湿蚀刻的方法形成，以形成倾斜的侧壁 和/或纹理。 可以控制TMAH蚀刻工艺的条件以形成粗糙或平滑侧壁的任何期望的组合。 因此，形成的模具具有比Si背面区域大的Si前侧和不垂直于模具的前表面或后表面的侧壁或侧边缘。 还描述了其它实施例。