公开(公告)号：US20120267714A1

公开(公告)日：2012-10-25

申请号：US13091578

申请日：2011-04-21

申请人： Rohit Dikshit ,  Mark L. Rinehimer ,  Michael D. Gruenhagen ,  Joseph A. Yedinak ,  Tracie Petersen ,  Ritu Sodhi ,  Dan Kinzer ,  Christopher L. Rexer ,  Fred Session

发明人： Rohit Dikshit ,  Mark L. Rinehimer ,  Michael D. Gruenhagen ,  Joseph A. Yedinak ,  Tracie Petersen ,  Ritu Sodhi ,  Dan Kinzer ,  Christopher L. Rexer ,  Fred Session

IPC分类号： H01L29/78 ,  H01L21/28

CPC分类号： H01L29/7813 ,  H01L24/05 ,  H01L29/41775 ,  H01L29/42372 ,  H01L29/7397 ,  H01L29/7455 ,  H01L29/7811 ,  H01L2224/04034 ,  H01L2224/04042 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2924/01327 ,  H01L2924/1301 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/01079 ,  H01L2924/00014 ,  H01L2924/01028 ,  H01L2924/01047 ,  H01L2924/01023 ,  H01L2924/01014 ,  H01L2924/01029 ,  H01L2924/00

摘要： This document discusses, among other things, a semiconductor device including a first metal layer coupled to a source region and a second metal layer coupled to a gate structure, wherein at least a portion of the first and second metal layers overlap vertically.

摘要翻译： 本文件尤其涉及包括耦合到源区的第一金属层和耦合到栅极结构的第二金属层的半导体器件，其中第一和第二金属层的至少一部分垂直重叠。

公开(公告)号：US08502313B2

公开(公告)日：2013-08-06

申请号：US13091578

申请日：2011-04-21

申请人： Rohit Dikshit ,  Mark L. Rinehimer ,  Michael D. Gruenhagen ,  Joseph A. Yedinak ,  Tracie Petersen ,  Ritu Sodhi ,  Dan Kinzer ,  Christopher L. Rexer ,  Fred C. Session

发明人： Rohit Dikshit ,  Mark L. Rinehimer ,  Michael D. Gruenhagen ,  Joseph A. Yedinak ,  Tracie Petersen ,  Ritu Sodhi ,  Dan Kinzer ,  Christopher L. Rexer ,  Fred C. Session

IPC分类号： H01L29/76

CPC分类号： H01L29/7813 ,  H01L24/05 ,  H01L29/41775 ,  H01L29/42372 ,  H01L29/7397 ,  H01L29/7455 ,  H01L29/7811 ,  H01L2224/04034 ,  H01L2224/04042 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2924/01327 ,  H01L2924/1301 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/01079 ,  H01L2924/00014 ,  H01L2924/01028 ,  H01L2924/01047 ,  H01L2924/01023 ,  H01L2924/01014 ,  H01L2924/01029 ,  H01L2924/00

摘要： This document discusses, among other things, a semiconductor device including a first metal layer coupled to a source region and a second metal layer coupled to a gate structure, wherein at least a portion of the first and second metal layers overlap vertically.

摘要翻译： 本文件尤其涉及包括耦合到源区的第一金属层和耦合到栅极结构的第二金属层的半导体器件，其中第一和第二金属层的至少一部分垂直重叠。

公开(公告)号：US20120273884A1

公开(公告)日：2012-11-01

申请号：US13095690

申请日：2011-04-27

申请人： Joseph A. Yedinak ,  Christopher L. Rexer ,  Mark L. Rinehimer ,  Praveen Muraleedharan Shenoy ,  Jaegil Lee ,  Hamza Yilmaz ,  Chongman Yun ,  Dwayne S. Reichl ,  James Pan ,  Rodney S. Ridley, SR. ,  Harold Heidenreich

发明人： Joseph A. Yedinak ,  Christopher L. Rexer ,  Mark L. Rinehimer ,  Praveen Muraleedharan Shenoy ,  Jaegil Lee ,  Hamza Yilmaz ,  Chongman Yun ,  Dwayne S. Reichl ,  James Pan ,  Rodney S. Ridley, SR. ,  Harold Heidenreich

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/0878 ,  H01L29/045 ,  H01L29/0634 ,  H01L29/0646 ,  H01L29/0649 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/404 ,  H01L29/42372 ,  H01L29/4238 ,  H01L29/66712 ,  H01L29/66734 ,  H01L29/7811 ,  H01L29/7813 ,  H01L29/872 ,  H01L29/8725

摘要： A power device includes a semiconductor region which in turn includes a plurality of alternately arranged pillars of first and second conductivity type. Each of the plurality of pillars of second conductivity type further includes a plurality of implant regions of the second conductivity type arranged on top of one another along the depth of pillars of second conductivity type, and a trench portion filled with semiconductor material of the second conductivity type directly above the plurality of implant regions of second conductivity type.

摘要翻译： 功率器件包括半导体区域，该半导体区域又包括多个交替布置的第一和第二导电类型的柱。 第二导电类型的多个柱中的每一个还包括沿着第二导电类型的柱的深度彼此顶部布置的多个第二导电类型的注入区，以及填充有第二导电类型的半导体材料的沟槽部 在第二导电类型的多个植入区域的正上方。

公开(公告)号：US20120273916A1

公开(公告)日：2012-11-01

申请号：US13095652

申请日：2011-04-27

申请人： Joseph A. Yedinak ,  Christopher L. Rexer ,  Mark L. Rinehimer ,  Praveen Muraleedharan Shenoy ,  Jaegil Lee ,  Hamza Yilmaz ,  Chongman Yun ,  Dwayne S. Reichl ,  James Pan ,  Rodney S. Ridley, SR. ,  Harold Heidenreich

发明人： Joseph A. Yedinak ,  Christopher L. Rexer ,  Mark L. Rinehimer ,  Praveen Muraleedharan Shenoy ,  Jaegil Lee ,  Hamza Yilmaz ,  Chongman Yun ,  Dwayne S. Reichl ,  James Pan ,  Rodney S. Ridley, SR. ,  Harold Heidenreich

IPC分类号： H01L29/872

CPC分类号： H01L29/0634 ,  H01L29/045 ,  H01L29/0615 ,  H01L29/0619 ,  H01L29/0649 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/404 ,  H01L29/4238 ,  H01L29/66712 ,  H01L29/66734 ,  H01L29/7397 ,  H01L29/74 ,  H01L29/7811 ,  H01L29/7813 ,  H01L29/872

摘要： A power device includes a semiconductor region which in turn includes a plurality of alternately arranged pillars of first and second conductivity type. Each of the plurality of pillars of second conductivity type further includes a plurality of implant regions of the second conductivity type arranged on top of one another along the depth of pillars of second conductivity type, and a trench portion filled with semiconductor material of the second conductivity type directly above the plurality of implant regions of second conductivity type.

公开(公告)号：US20100314707A1

公开(公告)日：2010-12-16

申请号：US12484096

申请日：2009-06-12

申请人： Joseph A. Yedinak ,  Mark L. Rinehimer ,  Thomas E. Grebs ,  John L. Benjamin

发明人： Joseph A. Yedinak ,  Mark L. Rinehimer ,  Thomas E. Grebs ,  John L. Benjamin

IPC分类号： H01L29/872 ,  H01L21/22 ,  H01L21/33

CPC分类号： H01L29/407 ,  H01L29/36 ,  H01L29/8725

摘要： Disclosed are semiconductor devices and methods of making semiconductor devices. An exemplary embodiment comprises a semiconductor layer of a first conductivity type having a first surface, a second surface, and a graded net doping concentration of the first conductivity type within a portion of the semiconductor layer. The graded portion is located adjacent to the top surface of the semiconductor layer, and the graded net doping concentration therein decreasing in value with distance from the top surface of the semiconductor layer. The exemplary device also comprises an electrode disposed at the first surface of the semiconductor layer and adjacent to the graded portion.

摘要翻译： 公开了制造半导体器件的半导体器件和方法。 示例性实施例包括第一导电类型的半导体层，其具有在半导体层的一部分内的第一导电类型的第一表面，第二表面和等级净掺杂浓度。 分级部分位于与半导体层的顶表面相邻的位置，并且其中的渐变网络掺杂浓度随距离半导体层的顶表面的距离而减小。 示例性器件还包括设置在半导体层的第一表面并且与渐变部分相邻的电极。

公开(公告)号：US06831329B2

公开(公告)日：2004-12-14

申请号：US10278224

申请日：2002-10-22

申请人： Joseph A. Yedinak ,  Jon Gladish ,  Sampat Shekhawat ,  Gary M. Dolny ,  Praveen Muraleedharan Shenoy ,  Douglas Joseph Lange ,  Mark L. Rinehimer

发明人： Joseph A. Yedinak ,  Jon Gladish ,  Sampat Shekhawat ,  Gary M. Dolny ,  Praveen Muraleedharan Shenoy ,  Douglas Joseph Lange ,  Mark L. Rinehimer

IPC分类号： H01L21336

CPC分类号： H01L29/4232 ,  H01L29/1095 ,  H01L29/66333 ,  H01L29/7395

摘要： A quick punch-through integrated gate bipolar transistor (IGBT) includes a drift region and a gate. The drift region has a drift region dopant concentration and a drift region thickness. The gate has a gate capacitance. The drift region dopant concentration, drift region thickness and gate capacitance are adjusted dependent at least in part upon the PNP gain of the IGBT to maintain the potential difference between the gate and emitter at a level greater than the IGBT threshold voltage when the collector voltage reaches the bus voltage. This insures that the hole carrier concentration remains approximately equal to or greater than the drift region dopant concentration when the depletion layer punches through to the buffer region during the turn-off delay. Thus, the collector voltage overshoot and the rate of change of voltage and current are controlled, and electromagnetic interference is reduced, during turn off.

摘要翻译： 快速穿透式集成栅双极晶体管（IGBT）包括漂移区和栅极。 漂移区具有漂移区掺杂浓度和漂移区厚度。 栅极具有栅极电容。 调整漂移区掺杂浓度，漂移区厚度和栅极电容至少部分依赖于IGBT的PNP增益，以在集电极电压达到时将栅极和发射极之间的电位差维持在大于IGBT阈值电压的电平 总线电压。 这确保当在关断延迟期间耗尽层冲击到缓冲区域时，空穴载流子浓度保持近似等于或大于漂移区掺杂剂浓度。 因此，控制集电极电压过冲和电压和电流的变化率，并且在关断期间电磁干扰降低。

公开(公告)号：US08673700B2

公开(公告)日：2014-03-18

申请号：US13095678

申请日：2011-04-27

申请人： Joseph A. Yedinak ,  Mark L. Rinehimer ,  Praveen Muraleedharan Shenoy

发明人： Joseph A. Yedinak ,  Mark L. Rinehimer ,  Praveen Muraleedharan Shenoy

IPC分类号： H01L21/00 ,  H01L21/84

CPC分类号： H01L29/7813 ,  H01L29/045 ,  H01L29/0615 ,  H01L29/0619 ,  H01L29/0623 ,  H01L29/0634 ,  H01L29/0649 ,  H01L29/0692 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/404 ,  H01L29/42372 ,  H01L29/66734 ,  H01L29/7811 ,  H01L29/872

摘要： A power device includes a semiconductor region which in turn includes a plurality of alternately arranged pillars of first and second conductivity type. Each of the plurality of pillars of second conductivity type further includes a plurality of implant regions of the second conductivity type arranged on top of one another along the depth of pillars of second conductivity type, and a trench portion filled with semiconductor material of the second conductivity type directly above the plurality of implant regions of second conductivity type.

公开(公告)号：US20120273875A1

公开(公告)日：2012-11-01

申请号：US13095670

申请日：2011-04-27

申请人： Joseph A. Yedinak ,  Mark L. Rinehimer ,  Praveen Muraleedharan Shenoy ,  Hamza Yilmaz ,  James Pan ,  Rodney S. Ridley

发明人： Joseph A. Yedinak ,  Mark L. Rinehimer ,  Praveen Muraleedharan Shenoy ,  Hamza Yilmaz ,  James Pan ,  Rodney S. Ridley

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/7813 ,  H01L21/0243 ,  H01L21/02579 ,  H01L29/045 ,  H01L29/0619 ,  H01L29/0634 ,  H01L29/0649 ,  H01L29/0692 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/404 ,  H01L29/42372 ,  H01L29/4238 ,  H01L29/66136 ,  H01L29/66143 ,  H01L29/66734 ,  H01L29/7811 ,  H01L29/8611 ,  H01L29/872

摘要： A power device includes a semiconductor region which in turn includes a plurality of alternately arranged pillars of first and second conductivity type. Each of the plurality of pillars of second conductivity type further includes a plurality of implant regions of the second conductivity type arranged on top of one another along the depth of pillars of second conductivity type, and a trench portion filled with semiconductor material of the second conductivity type directly above the plurality of implant regions of second conductivity type.

公开(公告)号：US08836028B2

公开(公告)日：2014-09-16

申请号：US13095690

申请日：2011-04-27

申请人： Joseph A. Yedinak ,  Mark L. Rinehimer ,  Praveen Muraleedharan Shenoy ,  Jaegil Lee ,  Dwayne S. Reichl ,  Harold Heidenreich

发明人： Joseph A. Yedinak ,  Mark L. Rinehimer ,  Praveen Muraleedharan Shenoy ,  Jaegil Lee ,  Dwayne S. Reichl ,  Harold Heidenreich

IPC分类号： H01L29/78 ,  H01L29/08 ,  H01L29/06 ,  H01L29/40

CPC分类号： H01L29/0878 ,  H01L29/045 ,  H01L29/0634 ,  H01L29/0646 ,  H01L29/0649 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/404 ,  H01L29/42372 ,  H01L29/4238 ,  H01L29/66712 ,  H01L29/66734 ,  H01L29/7811 ,  H01L29/7813 ,  H01L29/872 ,  H01L29/8725

摘要： In a general aspect, a power device can include at least one N-type epitaxial layer disposed on a substrate and a plurality of N-pillars and P-pillars that define alternating P-N-pillars in the at least one N-type epitaxial layer. The power device can also include an active region and a termination region, where the termination region surrounds the active region. The alternating P-N-pillars can be disposed in both the active region and the termination region, where the termination region can include a predetermined number of floating P-pillars.

摘要翻译： 在一般方面，功率器件可以包括设置在衬底上的至少一个N型外延层和在所述至少一个N型外延层中限定交替的P-N柱的多个N柱和P柱。 功率器件还可以包括有源区和端接区，其中终端区围绕有源区。 交替的P-N柱可以设置在有源区域和终止区域中，其中终止区域可以包括预定数量的浮动P柱。

公开(公告)号：US08772868B2

公开(公告)日：2014-07-08

申请号：US13095670

申请日：2011-04-27

申请人： Joseph A. Yedinak ,  Mark L. Rinehimer ,  Praveen Muraleedharan Shenoy ,  Hamza Yilmaz ,  James Pan ,  Rodney S. Ridley, Sr.

发明人： Joseph A. Yedinak ,  Mark L. Rinehimer ,  Praveen Muraleedharan Shenoy ,  Hamza Yilmaz ,  James Pan ,  Rodney S. Ridley, Sr.

IPC分类号： H01L29/66

CPC分类号： H01L29/7813 ,  H01L21/0243 ,  H01L21/02579 ,  H01L29/045 ,  H01L29/0619 ,  H01L29/0634 ,  H01L29/0649 ,  H01L29/0692 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/404 ,  H01L29/42372 ,  H01L29/4238 ,  H01L29/66136 ,  H01L29/66143 ,  H01L29/66734 ,  H01L29/7811 ,  H01L29/8611 ,  H01L29/872

摘要： A power device includes a semiconductor substrate having a plurality of alternately arranged pillars of first and second conductivity types. At least one of the plurality of pillars of second conductivity type includes a first trench epitaxial layer of the second conductivity type disposed on a trench sidewall of the second trench and a trench bottom surface of the second trench, a second trench epitaxial layer of the second conductivity type disposed on the first trench epitaxial layer of the second conductivity type, and an insulating material layer disposed on the second trench epitaxial layer of the second conductivity type.

摘要翻译： 功率器件包括具有多个交替布置的第一和第二导电类型的柱的半导体衬底。 第二导电类型的多个支柱中的至少一个包括设置在第二沟槽的沟槽侧壁上的第二导电类型的第一沟槽外延层和第二沟槽的沟槽底表面，第二沟槽外延层的第二沟槽外延层 设置在第二导电类型的第一沟槽外延层上的导电类型，以及设置在第二导电类型的第二沟槽外延层上的绝缘材料层。