公开(公告)号：US08502313B2

公开(公告)日：2013-08-06

申请号：US13091578

申请日：2011-04-21

申请人： Rohit Dikshit ,  Mark L. Rinehimer ,  Michael D. Gruenhagen ,  Joseph A. Yedinak ,  Tracie Petersen ,  Ritu Sodhi ,  Dan Kinzer ,  Christopher L. Rexer ,  Fred C. Session

发明人： Rohit Dikshit ,  Mark L. Rinehimer ,  Michael D. Gruenhagen ,  Joseph A. Yedinak ,  Tracie Petersen ,  Ritu Sodhi ,  Dan Kinzer ,  Christopher L. Rexer ,  Fred C. Session

IPC分类号： H01L29/76

CPC分类号： H01L29/7813 ,  H01L24/05 ,  H01L29/41775 ,  H01L29/42372 ,  H01L29/7397 ,  H01L29/7455 ,  H01L29/7811 ,  H01L2224/04034 ,  H01L2224/04042 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2924/01327 ,  H01L2924/1301 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/01079 ,  H01L2924/00014 ,  H01L2924/01028 ,  H01L2924/01047 ,  H01L2924/01023 ,  H01L2924/01014 ,  H01L2924/01029 ,  H01L2924/00

摘要： This document discusses, among other things, a semiconductor device including a first metal layer coupled to a source region and a second metal layer coupled to a gate structure, wherein at least a portion of the first and second metal layers overlap vertically.

摘要翻译： 本文件尤其涉及包括耦合到源区的第一金属层和耦合到栅极结构的第二金属层的半导体器件，其中第一和第二金属层的至少一部分垂直重叠。

公开(公告)号：US20120267714A1

公开(公告)日：2012-10-25

申请号：US13091578

申请日：2011-04-21

申请人： Rohit Dikshit ,  Mark L. Rinehimer ,  Michael D. Gruenhagen ,  Joseph A. Yedinak ,  Tracie Petersen ,  Ritu Sodhi ,  Dan Kinzer ,  Christopher L. Rexer ,  Fred Session

发明人： Rohit Dikshit ,  Mark L. Rinehimer ,  Michael D. Gruenhagen ,  Joseph A. Yedinak ,  Tracie Petersen ,  Ritu Sodhi ,  Dan Kinzer ,  Christopher L. Rexer ,  Fred Session

IPC分类号： H01L29/78 ,  H01L21/28

CPC分类号： H01L29/7813 ,  H01L24/05 ,  H01L29/41775 ,  H01L29/42372 ,  H01L29/7397 ,  H01L29/7455 ,  H01L29/7811 ,  H01L2224/04034 ,  H01L2224/04042 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2924/01327 ,  H01L2924/1301 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/01079 ,  H01L2924/00014 ,  H01L2924/01028 ,  H01L2924/01047 ,  H01L2924/01023 ,  H01L2924/01014 ,  H01L2924/01029 ,  H01L2924/00

摘要： This document discusses, among other things, a semiconductor device including a first metal layer coupled to a source region and a second metal layer coupled to a gate structure, wherein at least a portion of the first and second metal layers overlap vertically.

摘要翻译： 本文件尤其涉及包括耦合到源区的第一金属层和耦合到栅极结构的第二金属层的半导体器件，其中第一和第二金属层的至少一部分垂直重叠。

公开(公告)号：US08072027B2

公开(公告)日：2011-12-06

申请号：US12480065

申请日：2009-06-08

申请人： Suku Kim ,  Dan Calafut ,  Ihsiu Ho ,  Dan Kinzer ,  Steven Sapp ,  Ashok Challa ,  Seokjin Jo ,  Mark Larsen

发明人： Suku Kim ,  Dan Calafut ,  Ihsiu Ho ,  Dan Kinzer ,  Steven Sapp ,  Ashok Challa ,  Seokjin Jo ,  Mark Larsen

IPC分类号： H01L29/78

CPC分类号： H01L29/7813 ,  H01L29/0865 ,  H01L29/407 ,  H01L29/4236 ,  H01L29/4933

摘要： Semiconductor devices and methods for making such devices that contain a 3D channel architecture are described. The 3D channel architecture is formed using a dual trench structure containing with a plurality of lower trenches extending in an x and y directional channels and separated by a mesa and an upper trench extending in a y direction and located in an upper portion of the substrate proximate a source region. Thus, smaller pillar trenches are formed within the main line-shaped trench. Such an architecture generates additional channel regions which are aligned substantially perpendicular to the conventional line-shaped channels. The channel regions, both conventional and perpendicular, are electrically connected by their corner and top regions to produce higher current flow in all three dimensions. With such a configuration, higher channel density, a stronger inversion layer, and a more uniform threshold distribution can be obtained for the semiconductor device. Other embodiments are described.

摘要翻译： 描述了用于制造包含3D通道架构的这种设备的半导体器件和方法。 3D通道架构使用双沟槽结构形成，该双沟槽结构包含多个下沟槽，该多个下沟槽在x和y定向沟槽中延伸并且被台面和上部沟槽隔开，该沟槽沿ay方向延伸并且位于基板的上部附近 源区。 因此，在主线状沟槽内形成较小的支柱沟槽。 这种架构产生基本垂直于常规线形通道排列的附加通道区域。 常规和垂直的通道区域通过其角部和顶部区域电连接以在所有三维空间中产生更高的电流。 通过这样的结构，半导体器件可以获得更高的沟道密度，更强的反转层和更均匀的阈值分布。 描述其他实施例。

公开(公告)号：US20120088331A1

公开(公告)日：2012-04-12

申请号：US13323979

申请日：2011-12-13

申请人： Dan Kinzer ,  Yong Liu ,  Stephen Martin

发明人： Dan Kinzer ,  Yong Liu ,  Stephen Martin

IPC分类号： H01L21/50

CPC分类号： H01L25/16 ,  H01L21/76898 ,  H01L23/5389 ,  H01L24/16 ,  H01L2224/0401 ,  H01L2224/05025 ,  H01L2224/131 ,  H01L2224/17106 ,  H01L2924/01029 ,  H01L2924/01068 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/014 ,  H01L2924/00

摘要： This document discusses, among other things, apparatus and methods for an IC package including first and a second discrete components fabricated into a semiconductor substrate. The first and second discrete components can be adjacent to one another in the semiconductor substrate, and an integrated circuit die can be mounted on the semiconductor substrate and coupled to the first and second discrete components.

摘要翻译： 本文件尤其涉及包括制造在半导体衬底中的第一和第二分立组件的IC封装的装置和方法。 第一和第二分立组件可以在半导体衬底中彼此相邻，并且集成电路管芯可以安装在半导体衬底上并耦合到第一和第二分立组件。

公开(公告)号：US08211747B2

公开(公告)日：2012-07-03

申请号：US13323979

申请日：2011-12-13

申请人： Dan Kinzer ,  Yong Liu ,  Stephen Martin

发明人： Dan Kinzer ,  Yong Liu ,  Stephen Martin

IPC分类号： H01L21/00

CPC分类号： H01L25/16 ,  H01L21/76898 ,  H01L23/5389 ,  H01L24/16 ,  H01L2224/0401 ,  H01L2224/05025 ,  H01L2224/131 ,  H01L2224/17106 ,  H01L2924/01029 ,  H01L2924/01068 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/014 ,  H01L2924/00

摘要： This document discusses, among other things, apparatus and methods for an IC package including first and a second discrete components fabricated into a semiconductor substrate. The first and second discrete components can be adjacent to one another in the semiconductor substrate, and an integrated circuit die can be mounted on the semiconductor substrate and coupled to the first and second discrete components.

摘要翻译： 本文件尤其涉及包括制造在半导体衬底中的第一和第二分立组件的IC封装的装置和方法。 第一和第二分立组件可以在半导体衬底中彼此相邻，并且集成电路管芯可以安装在半导体衬底上并耦合到第一和第二分立组件。

公开(公告)号：US6040626A

公开(公告)日：2000-03-21

申请号：US225153

申请日：1999-01-04

申请人： Chuan Cheah ,  Jorge Munoz ,  Dan Kinzer

发明人： Chuan Cheah ,  Jorge Munoz ,  Dan Kinzer

IPC分类号： H01L21/60 ,  H01L23/48 ,  H01L23/495 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L24/40 ,  H01L23/49562 ,  H01L24/36 ,  H01L2224/05599 ,  H01L2224/0603 ,  H01L2224/32245 ,  H01L2224/37011 ,  H01L2224/40091 ,  H01L2224/40095 ,  H01L2224/40245 ,  H01L2224/45015 ,  H01L2224/48091 ,  H01L2224/4813 ,  H01L2224/48247 ,  H01L2224/4846 ,  H01L2224/48465 ,  H01L2224/48472 ,  H01L2224/73221 ,  H01L2224/73265 ,  H01L2224/85439 ,  H01L2224/85444 ,  H01L2224/8547 ,  H01L24/45 ,  H01L24/48 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/1301 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/30107

摘要： A semiconductor package includes a bottom leadframe having a bottom plate portion and at least one first terminal extending from the bottom plate portion; at least one second terminal being co-planar with the first terminal; a semiconductor power MOSFET die having a bottom surface defining a drain connection and a top surface on which a first metalized region defining a source and a second metalized region defining a gate are disposed, the bottom surface being coupled to the bottom plate of the leadframe such that the first terminal is electrically connected to the drain; a copper plate coupled to and spanning a substantial part of the first metalized region defining the source connection; and at least one beam portion being sized and shaped to couple the copper plate portion to the at least one second terminal such that it is electrically coupled to the source.

摘要翻译： 半导体封装包括具有底板部分的底部引线框架和从底板部分延伸的至少一个第一端子; 至少一个第二端子与所述第一端子共面; 具有限定漏极连接的底表面的半导体功率MOSFET管芯和顶表面，其上限定限定源极的第一金属化区域和限定栅极的第二金属化区域，所述底表面联接到引线框架的底板， 第一端子电连接到漏极; 铜板，其耦合并跨越限定所述源连接的所述第一金属化区域的主要部分; 并且至少一个梁部分的尺寸和形状被设计成将铜板部分耦合到至少一个第二端子，使得它被电耦合到源极。

公开(公告)号：US08115260B2

公开(公告)日：2012-02-14

申请号：US12683058

申请日：2010-01-06

申请人： Dan Kinzer ,  Yong Liu ,  Stephen Martin

发明人： Dan Kinzer ,  Yong Liu ,  Stephen Martin

IPC分类号： H01L27/088

CPC分类号： H01L25/16 ,  H01L21/76898 ,  H01L23/5389 ,  H01L24/16 ,  H01L2224/0401 ,  H01L2224/05025 ,  H01L2224/131 ,  H01L2224/17106 ,  H01L2924/01029 ,  H01L2924/01068 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/014 ,  H01L2924/00

摘要： This document discusses, among other things, an IC package including first and a second discrete components fabricated into a semiconductor substrate. The first and second discrete components can be adjacent to one another in the semiconductor substrate, and an integrated circuit die can be mounted on the semiconductor substrate and coupled to the first and second discrete components.

摘要翻译： 本文件尤其讨论了包括制造在半导体衬底中的第一和第二分立组件的IC封装。 第一和第二分立组件可以在半导体衬底中彼此相邻，并且集成电路管芯可以安装在半导体衬底上并耦合到第一和第二分立组件。

公开(公告)号：US20110163391A1

公开(公告)日：2011-07-07

申请号：US12683058

申请日：2010-01-06

申请人： Dan Kinzer ,  Yong Liu ,  Stephen Martin

发明人： Dan Kinzer ,  Yong Liu ,  Stephen Martin

IPC分类号： H01L23/538 ,  H01L27/088 ,  H01L21/60

CPC分类号： H01L25/16 ,  H01L21/76898 ,  H01L23/5389 ,  H01L24/16 ,  H01L2224/0401 ,  H01L2224/05025 ,  H01L2224/131 ,  H01L2224/17106 ,  H01L2924/01029 ,  H01L2924/01068 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/014 ,  H01L2924/00

摘要： This document discusses, among other things, an IC package including first and a second discrete components fabricated into a semiconductor substrate. The first and second discrete components can be adjacent to one another in the semiconductor substrate, and an integrated circuit die can be mounted on the semiconductor substrate and coupled to the first and second discrete components.

摘要翻译： 本文件尤其讨论了包括制造在半导体衬底中的第一和第二分立组件的IC封装。 第一和第二分立组件可以在半导体衬底中彼此相邻，并且集成电路管芯可以安装在半导体衬底上并耦合到第一和第二分立组件。

公开(公告)号：US20100308402A1

公开(公告)日：2010-12-09

申请号：US12480065

申请日：2009-06-08

申请人： Suku Kim ,  Dan Calafut ,  Ihsiu Ho ,  Dan Kinzer ,  Steven Sapp ,  Ashok Challa ,  Seokjin Jo ,  Mark Larsen

发明人： Suku Kim ,  Dan Calafut ,  Ihsiu Ho ,  Dan Kinzer ,  Steven Sapp ,  Ashok Challa ,  Seokjin Jo ,  Mark Larsen

IPC分类号： H01L29/78

CPC分类号： H01L29/7813 ,  H01L29/0865 ,  H01L29/407 ,  H01L29/4236 ,  H01L29/4933

摘要： Semiconductor devices and methods for making such devices that contain a 3D channel architecture are described. The 3D channel architecture is formed using a dual trench structure containing with a plurality of lower trenches extending in an x and y directional channels and separated by a mesa and an upper trench extending in a y direction and located in an upper portion of the substrate proximate a source region. Thus, smaller pillar trenches are formed within the main line-shaped trench. Such an architecture generates additional channel regions which are aligned substantially perpendicular to the conventional line-shaped channels. The channel regions, both conventional and perpendicular, are electrically connected by their corner and top regions to produce higher current flow in all three dimensions. With such a configuration, higher channel density, a stronger inversion layer, and a more uniform threshold distribution can be obtained for the semiconductor device. Other embodiments are described.

摘要翻译： 描述了用于制造包含3D通道架构的这种设备的半导体器件和方法。 3D通道架构使用双沟槽结构形成，该双沟槽结构包含多个下沟槽，该多个下沟槽在x和y定向沟槽中延伸并且被台面和上部沟槽隔开，该沟槽沿ay方向延伸并且位于基板的上部附近 源区。 因此，在主线状沟槽内形成较小的支柱沟槽。 这种架构产生基本垂直于常规线形通道排列的附加通道区域。 常规和垂直的通道区域通过其角部和顶部区域电连接以在所有三维空间中产生更高的电流。 通过这样的结构，半导体器件可以获得更高的沟道密度，更强的反转层和更均匀的阈值分布。 描述其他实施例。