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    Circuit configuration with a memory array
    2.
    发明授权
    Circuit configuration with a memory array 有权

    公开(公告)号：US06614700B2

    公开(公告)日：2003-09-02

    申请号：US10116826

    申请日：2002-04-05

    申请人： Stefan Dietrich ,  Peter Schrögmeier ,  Sabine Kieser ,  Christian Weis

    发明人： Stefan Dietrich ,  Peter Schrögmeier ,  Sabine Kieser ,  Christian Weis

    IPC分类号： G11C700

    CPC分类号： G11C7/109 ,  G11C7/1078 ,  G11C7/22

    摘要： The circuit configuration has a memory array, a memory access controller, a control unit, and an input/output circuit. The control unit outputs a control signal simultaneously to the memory access controller and to the input/output circuit. When the control signal is received, the input/output circuit outputs data to the memory access controller via the data bus. When the control signal is received, the memory access controller stores the data present on the data bus in memory cells of the memory array. Owing to different geometric arrangements and different electrical capacitances, differences in propagation time of the control signals may occur on the path from the control unit to the memory access controller and from the control unit to the input/output circuit. For this purpose, a delay circuit or delay line is provided on the signal path to the memory access controller which brings about a delay of the control signal. This enables precise synchronization of the writing of data into the memory array.

    Integrated memory, and a method of operating an integrated memory
    4.
    发明授权
    Integrated memory, and a method of operating an integrated memory 失效
    集成存储器以及操作集成存储器的方法

    公开(公告)号：US06882554B2

    公开(公告)日：2005-04-19

    申请号：US10287501

    申请日：2002-11-04

    申请人： Michael Markert ,  Christian Weis ,  Sabine Kieser ,  Stefan Dietrich ,  Peter Schrögmeier ,  Thomas Hein

    发明人： Michael Markert ,  Christian Weis ,  Sabine Kieser ,  Stefan Dietrich ,  Peter Schrögmeier ,  Thomas Hein

    IPC分类号： G11C7/06 ,  G11C11/408 ,  G11C11/4091 ,  G11C5/06

    CPC分类号： G11C7/067 ,  G11C11/4087 ,  G11C11/4091 ,  G11C2207/105

    摘要： An integrated memory has row lines, column lines and column selection lines for activating read/write amplifiers. In each case, one group of a predetermined number of memory cells belongs to a row and a column address. Furthermore, the memory has a number of connecting pads corresponding to the predetermined number. Each memory cell in a group of memory cells is associated with one of the connecting pads. A control circuit for controlling the memory access is designed and can be operated such that, with a column address, it activates at least two different column selection lines. One of the column selection lines is activated for two or more column addresses. The delay times and the line lengths on the memory chip can thus be reduced in size.

    摘要翻译： 集成存储器具有用于激活读/写放大器的行线，列线和列选择线。 在每种情况下，一组预定数量的存储单元属于行和列地址。 此外，存储器具有对应于预定数量的多个连接焊盘。 一组存储器单元中的每个存储器单元与一个连接焊盘相关联。 设计用于控制存储器访问的控制电路，并且可以操作该控制电路，使得通过列地址激活至少两个不同的列选择线。 对于两个或更多列地址，其中一列列选择行被激活。 因此，可以减小存储芯片上的延迟时间和线路长度。

    Latency time switch for an S-DRAM
    5.
    发明授权
    Latency time switch for an S-DRAM 失效
    S-DRAM的延迟时间切换

    公开(公告)号：US06804165B2

    公开(公告)日：2004-10-12

    申请号：US10374657

    申请日：2003-02-26

    申请人： Peter Schrögmeier ,  Stefan Dietrich ,  Sabine Kieser ,  Pramod Acharya

    发明人： Peter Schrögmeier ,  Stefan Dietrich ,  Sabine Kieser ,  Pramod Acharya

    IPC分类号： G11C800

    CPC分类号： G11C7/222 ,  G11C7/1072 ,  G11C7/22 ,  G11C11/4076

    摘要： Latency time circuit for an S-DRAM (1), which is clocked by a high-frequency clock signal (CLK), for producing a delayed data enable signal for synchronous data transfer through a data path (38) of the S-DRAM (1), having a controllable latency time generator (57) for delaying a decoded external data enable signal (PAR) with an adjustable latency time, which a comparison circuit (60) which compares a cycle time (tcycle) of the high-frequency clock signal (CLK) with a predetermined signal delay time of the data path (38), and reduces the latency time of the latency time generator (57) by the cycle time if the signal delay time of the data path (38) is greater than the cycle time (tcycle) of the clock signal (CLK)

    摘要翻译： 用于产生用于通过S-DRAM的数据路径（38）进行同步数据传输的延迟数据使能信号的用于由高频时钟信号（CLK）计时的S-DRAM（1）的延迟时间电路 具有可控等待时间发生器（57），用于以可调延迟时间延迟解码的外部数据使能信号（PAR），比较电路（60）比较高频时钟的周期时间（tcycle） 信号（CLK），具有所述数据路径（38）的预定信号延迟时间，并且如果所述数据路径（38）的信号延迟时间大于所述延迟时间，则将所述等待时间发生器（57）的等待时间缩短循环时间 时钟信号（CLK）的周期时间（tcycle）

    Method and circuit configuration for read-write mode control of a synchronous memory
    6.
    发明授权
    Method and circuit configuration for read-write mode control of a synchronous memory 有权
    用于同步存储器的读写模式控制的方法和电路配置

    公开(公告)号：US06359832B2

    公开(公告)日：2002-03-19

    申请号：US09773222

    申请日：2001-01-31

    申请人： Stefan Dietrich ,  Sabine Schöniger ,  Peter Schrögmeier ,  Christian Weis

    发明人： Stefan Dietrich ,  Sabine Schöniger ,  Peter Schrögmeier ,  Christian Weis

    IPC分类号： G11C800

    CPC分类号： G11C7/1072 ,  G11C7/12 ,  G11C11/4094

    摘要： A read-write mode control method is described in which a waiting time during a reading process can be shortened by conducting a read instruction with auto-precharging in a first circuit part. The first circuit part is separate from a second circuit part used for conducting the write instruction, since a memory controller does not need to insert any wait cycles between a write instruction and an associated activate signal.

    摘要翻译： 描述了一种读写模式控制方法，其中可以通过在第一电路部分中进行具有自动预充电的读取指令来缩短读取处理期间的等待时间。 第一电路部分与用于执行写指令的第二电路部分分开，因为存储器控制器不需要在写指令和相关联的激活信号之间插入任何等待周期。

    Integrated memory with row access control to activate and precharge row lines, and method of operating such a memory
    7.
    发明授权
    Integrated memory with row access control to activate and precharge row lines, and method of operating such a memory 有权
    具有行访问控制的集成存储器，用于激活和预充行行，以及操作这种存储器的方法

    公开(公告)号：US06396755B2

    公开(公告)日：2002-05-28

    申请号：US09864978

    申请日：2001-05-24

    申请人： Stefan Dietrich ,  Sabine Schöniger ,  Peter Schrögmeier ,  Christian Weis

    发明人： Stefan Dietrich ,  Sabine Schöniger ,  Peter Schrögmeier ,  Christian Weis

    IPC分类号： G11C700

    CPC分类号： G11C8/00

    摘要： An integrated memory has memory cells which are each connected to a row line to select one of the memory cells and to a column line to read or write a data signal. A row access controller is used to activate one of the row lines to select one of the memory cells and to control a precharging operation to precharge one of the row lines. A precharge command initiates a precharging operation. The precharging operation for an activated row line is triggered by the row access controller when the reading or writing of a data signal has been finished and when a defined time interval, during which the row line must at least be activated, has elapsed since the activation. As a result, a precharging operation of the activated row line is controlled in a self-adjusting manner. A method of operating an integrated memory is also provided.

    摘要翻译： 集成存储器具有各自连接到行线的存储单元，以选择存储器单元之一和列线来读取或写入数据信号。 行访问控制器用于激活行行之一以选择存储器单元之一并且控制预充电操作以对行行之一进行预充电。 预充电命令启动预充电操作。 激活的行线的预充电操作在数据信号的读取或写入已经完成时由行存取控制器触发，并且当激活行至少必须被激活的定义的时间间隔已经过去时 。 结果，以自动调节的方式控制激活的行线的预充电操作。 还提供了一种操作集成存储器的方法。

    Integrated circuit having a command decoder
    10.
    发明授权
    Integrated circuit having a command decoder 有权
    具有命令解码器的集成电路

    公开(公告)号：US06404699B1

    公开(公告)日：2002-06-11

    申请号：US09603742

    申请日：2000-06-26

    申请人： Peter Schrögmeier ,  Stefan Dietrich ,  Sabine Schöniger ,  Christian Weis

    发明人： Peter Schrögmeier ,  Stefan Dietrich ,  Sabine Schöniger ,  Christian Weis

    IPC分类号： G11C800

    CPC分类号： G11C7/22 ,  G11C7/1045 ,  G11C11/4076

    摘要： The integrated circuit has an activation decoder whose outputs are connected to the inputs of a command decoder. When an activation signal is at a first logic level, the activation decoder produces at its outputs a command supplied to it from command inputs. When the activation signal is at a second logic level, the activation decoder produces a deactivation command at its outputs irrespective of the command supplied to it from the command inputs. The command decoder does not activate any of its outputs when the deactivation command is being supplied to its inputs. The command decoder activates one of its outputs in each case when a different command is supplied to its inputs.

    摘要翻译： 集成电路具有激活解码器，其输出端连接到命令解码器的输入端。 当激活信号处于第一逻辑电平时，激活解码器在其输出端产生从命令输入提供给它的命令。 当激活信号处于第二逻辑电平时，激活解码器在其输出处产生停用命令，而与从命令输入提供给其的命令无关。 当向其输入提供停用命令时，命令解码器不会激活其任何输出。 当向其输入提供不同的命令时，命令解码器在每种情况下激活其一个输出。