公开(公告)号：US20130330843A1

公开(公告)日：2013-12-12

申请号：US13490740

申请日：2012-06-07

申请人： Michael P. Chudzik ,  Min Dai ,  Jinping Liu ,  Paul A. Ronsheim ,  Joseph F. Shepard, JR. ,  Shahab Siddiqui

发明人： Michael P. Chudzik ,  Min Dai ,  Jinping Liu ,  Paul A. Ronsheim ,  Joseph F. Shepard, JR. ,  Shahab Siddiqui

IPC分类号： H01L21/66 ,  G06F17/50

CPC分类号： H01L29/513 ,  H01L21/28185 ,  H01L21/28202 ,  H01L22/12 ,  H01L22/26 ,  H01L29/518 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of forming a semiconductor device is disclosed. The method includes: forming a dielectric region on a substrate; annealing the dielectric region in an environment including ammonia (NH3); monitoring a nitrogen peak of at least one of the substrate and the dielectric region during the annealing; and adjusting a parameter of the environment based on the monitoring of the nitrogen peak.

摘要翻译： 公开了一种形成半导体器件的方法。 该方法包括：在基板上形成电介质区域; 在包括氨（NH 3）在内的环境中退火电介质区域; 在退火期间监测所述衬底和所述电介质区域中的至少一个的氮峰; 并根据氮峰的监测来调整环境参数。

公开(公告)号：US20140001570A1

公开(公告)日：2014-01-02

申请号：US13537101

申请日：2012-06-29

申请人： MaryJane Brodsky ,  Michael P. Chudzik ,  Min Dai ,  Joseph F. Shepard, JR. ,  Shahab Siddiqui ,  Yanfeng Wang ,  Jinping Liu

发明人： MaryJane Brodsky ,  Michael P. Chudzik ,  Min Dai ,  Joseph F. Shepard, JR. ,  Shahab Siddiqui ,  Yanfeng Wang ,  Jinping Liu

IPC分类号： H01L27/088 ,  H01L21/31

CPC分类号： H01L21/02321 ,  H01L21/28194 ,  H01L21/3115 ,  H01L21/823462 ,  H01L29/513 ,  H01L29/517

摘要： A composite high dielectric constant (high-k) gate dielectric includes a stack of a doped high-k gate dielectric and an undoped high-k gate dielectric. The doped high-k gate dielectric can be formed by providing a stack of a first high-k dielectric material layer and a dopant metal layer and annealing the stack to induce the diffusion of the dopant metal into the first high-k dielectric material layer. The undoped high-k gate dielectric is formed by subsequently depositing a second high-k dielectric material layer. The composite high-k gate dielectric can provide an increased gate-leakage oxide thickness without increasing inversion oxide thickness.

摘要翻译： 复合高介电常数（high-k）栅极电介质包括掺杂的高k栅极电介质和未掺杂的高k栅极电介质的堆叠。 可以通过提供第一高k电介质材料层和掺杂剂金属层的堆叠来形成掺杂的高k栅极电介质，并且对叠层进行退火以引起掺杂剂金属扩散到第一高k电介质材料层中。 通过随后沉积第二高k电介质材料层形成未掺杂的高k栅极电介质。 复合高k栅极电介质可以提供增加的栅极 - 漏极氧化物厚度，而不增加反转氧化物厚度。

公开(公告)号：US20120329230A1

公开(公告)日：2012-12-27

申请号：US13164891

申请日：2011-06-21

申请人： Michael P. Chudzik ,  Min Dai ,  Joseph F. Shepard, JR. ,  Shahab Siddiqui ,  Jinping Liu

发明人： Michael P. Chudzik ,  Min Dai ,  Joseph F. Shepard, JR. ,  Shahab Siddiqui ,  Jinping Liu

IPC分类号： H01L21/336 ,  H01L21/31

CPC分类号： H01L21/02052 ,  H01L21/0214 ,  H01L21/02164 ,  H01L21/02238 ,  H01L21/02255 ,  H01L21/02301 ,  H01L21/02332 ,  H01L21/0234 ,  H01L21/28211 ,  H01L21/28238

摘要： A method of fabricating a silicon-containing oxide layer that includes providing a chemical oxide layer on a surface of a semiconductor substrate, removing the chemical oxide layer in an oxygen-free environment at a temperature of 1000° C. or greater to provide a bare surface of the semiconductor substrate, and introducing an oxygen-containing gas at a flow rate to the bare surface of the semiconductor substrate for a first time period at the temperature of 1000° C. The temperature is then reduced to room temperature during a second time period while maintaining the flow rate of the oxygen containing gas to provide a silicon-containing oxide layer having a thickness ranging from 0.5 Å to 10 Å.

摘要翻译： 一种制造含硅氧化物层的方法，包括在半导体衬底的表面上提供化学氧化物层，在1000℃或更高的温度下在无氧环境中除去化学氧化物层，以提供裸露 在半导体衬底的表面上，以1000℃的温度将半导体衬底的裸露表面的含氧气体首次引入半导体衬底的裸露表面。然后在第二时间内将温度降至室温 同时保持含氧气体的流速，从而提供厚度范围从0.5到10的含硅氧化物层。

公开(公告)号：US20130277765A1

公开(公告)日：2013-10-24

申请号：US13453131

申请日：2012-04-23

申请人： Michael P. Chudzik ,  Min Dai ,  Jinping Liu ,  Joseph F. Shepard, JR. ,  Keith Kwong Hon Wong

发明人： Michael P. Chudzik ,  Min Dai ,  Jinping Liu ,  Joseph F. Shepard, JR. ,  Keith Kwong Hon Wong

IPC分类号： H01L29/772 ,  H01L21/283

CPC分类号： H01L29/4966 ,  H01L21/28202 ,  H01L29/47 ,  H01L29/51 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518

摘要： A semiconductor device is disclosed. The semiconductor device includes a substrate; and a gate structure disposed directly on the substrate, the gate structure including: a graded region with a varied material concentration profile; and a metal layer disposed on the graded region.

摘要翻译： 公开了一种半导体器件。 半导体器件包括衬底; 以及栅极结构，其直接设置在所述基板上，所述栅极结构包括：具有不同材料浓度分布的渐变区域; 以及设置在分级区域上的金属层。

公开(公告)号：US20110169141A1

公开(公告)日：2011-07-14

申请号：US12685332

申请日：2010-01-11

申请人： Joseph F. Shepard, JR. ,  Siddarth A. Krishnan ,  Rishikesh Krishnan ,  Michael P. Chudzik

发明人： Joseph F. Shepard, JR. ,  Siddarth A. Krishnan ,  Rishikesh Krishnan ,  Michael P. Chudzik

IPC分类号： H01L23/00 ,  H01L21/316

CPC分类号： H01L21/02164 ,  H01L21/02326 ,  H01L21/02337 ,  H01L21/28185 ,  H01L21/28211 ,  H01L21/28255 ,  H01L21/823807 ,  H01L21/823857 ,  H01L29/66651

摘要： A method of creating insulating layers on different semiconductor materials includes providing a substrate having disposed thereon a first material and a second material, the second material having a chemical composition different from the first material; non-epitaxially depositing a continuous sacrificial layer of approximately constant thickness onto the first material and the second material, and then converting the sacrificial layer into a layer consisting essentially of SiO2 without oxidizing more than 10 angstroms into the second material. A structure includes a silicon nitride film disposed conformally on a silicon layer and a silicon germanium layer; a SiO2 layer is disposed on the silicon nitride film.

摘要翻译： 在不同半导体材料上制造绝缘层的方法包括提供其上设置有第一材料和第二材料的基底，所述第二材料具有与第一材料不同的化学组成; 将大约恒定厚度的连续牺牲层非外延沉积到第一材料和第二材料上，然后将牺牲层转变成基本上由SiO 2组成的层，而不将氧化物超过10埃，进入第二材料。 一种结构包括：保形地设置在硅层和硅锗层上的氮化硅膜; SiO 2层设置在氮化硅膜上。

公开(公告)号：US20120187453A1

公开(公告)日：2012-07-26

申请号：US13431537

申请日：2012-03-27

申请人： Joseph F. Shepard, JR. ,  Siddarth A. Krishnan ,  Rishikesh Krishnan ,  Michael P. Chudzik

发明人： Joseph F. Shepard, JR. ,  Siddarth A. Krishnan ,  Rishikesh Krishnan ,  Michael P. Chudzik

IPC分类号： H01L27/092

CPC分类号： H01L21/02164 ,  H01L21/02326 ,  H01L21/02337 ,  H01L21/28185 ,  H01L21/28211 ,  H01L21/28255 ,  H01L21/823807 ,  H01L21/823857 ,  H01L29/66651

摘要： A semiconductor structure is provided that includes a substrate having disposed thereon a silicon layer and a silicon germanium layer. An insulator is disposed between the silicon layer and the silicon germanium layer. An optional silicon nitride film is disposed conformally on the silicon layer and the silicon germanium layer, and a SiO2layer disposed on the optional silicon nitride film or on the silicon layer and the silicon germanium layer, when the optional silicon nitride film is not present.

摘要翻译： 提供一种半导体结构，其包括其上设置有硅层和硅锗层的衬底。 绝缘体设置在硅层和硅锗层之间。 当可选的氮化硅膜不存在时，可选择的氮化硅膜保形地设置在硅层和硅锗层上，以及设置在任选的氮化硅膜上或者硅层和硅锗层上的SiO 2层。

公开(公告)号：US20120196424A1

公开(公告)日：2012-08-02

申请号：US13017108

申请日：2011-01-31

申请人： Rishikesh Krishnan ,  Joseph F. Shepard, JR. ,  Michael P. Chudzik ,  Christian Lavoie ,  Dong-Ick Lee ,  Oh-Jung Kwon ,  Unoh Kwon ,  Youngjin Choi

发明人： Rishikesh Krishnan ,  Joseph F. Shepard, JR. ,  Michael P. Chudzik ,  Christian Lavoie ,  Dong-Ick Lee ,  Oh-Jung Kwon ,  Unoh Kwon ,  Youngjin Choi

IPC分类号： H01L21/02

CPC分类号： H01L27/1203 ,  H01L27/10829 ,  H01L27/1087 ,  H01L28/40 ,  H01L29/66181

摘要： A method includes providing an SOI substrate including a layer of silicon disposed atop a layer of an oxide, the layer of an oxide being disposed atop the semiconductor substrate; forming a deep trench having a sidewall extending through the layer of silicon and the layer of an oxide and into the substrate; depositing a continuous spacer on the sidewall to cover the layer of silicon, the layer of an oxide and a part of the substrate; depositing a first conformal layer of a conductive material throughout the inside of the deep trench; creating a silicide within the deep trench in regions extending through the sidewall into an uncovered part of the substrate; removing the first conformal layer from the continuous spacer; removing the continuous spacer; depositing a layer of a high k dielectric material throughout the inside of the deep trench, and depositing a second conformal layer of a conductive material onto the layer of a high-k dielectric material.

摘要翻译： 一种方法包括提供包括设置在氧化物层顶上的硅层的SOI衬底，所述氧化物层设置在所述半导体衬底的顶部; 形成具有延伸穿过所述硅层和所述氧化物层的侧壁并进入所述衬底的深沟槽; 在所述侧壁上沉积连续间隔物以覆盖所述硅层，所述氧化物层和所述衬底的一部分; 在深沟槽的整个内部沉积导电材料的第一共形层; 在穿过侧壁延伸到衬底的未覆盖部分的区域中的深沟槽内产生硅化物; 从所述连续间隔件中去除所述第一共形层; 去除连续间隔物; 在深沟槽的整个内部沉积高k介电材料层，以及将高导电材料的第二保形层沉积到高k电介质材料的层上。

公开(公告)号：US20080293259A1

公开(公告)日：2008-11-27

申请号：US12187767

申请日：2008-08-07

申请人： Wanda Andreoni ,  Alessandro C. Callegari ,  Eduard A. Cartier ,  Alessandro Curioni ,  Christopher P. D'Emic ,  Evgeni Gousev ,  Michael A. Gribelyuk ,  Paul C. Jamison ,  Rajarao Jammy ,  Dianne L. Lacey ,  Fenton R. McFeely ,  Vijay Narayanan ,  Carlo A. Pignedoli ,  Joseph F. Shepard, JR. ,  Sufi Zafar

发明人： Wanda Andreoni ,  Alessandro C. Callegari ,  Eduard A. Cartier ,  Alessandro Curioni ,  Christopher P. D'Emic ,  Evgeni Gousev ,  Michael A. Gribelyuk ,  Paul C. Jamison ,  Rajarao Jammy ,  Dianne L. Lacey ,  Fenton R. McFeely ,  Vijay Narayanan ,  Carlo A. Pignedoli ,  Joseph F. Shepard, JR. ,  Sufi Zafar

IPC分类号： H01L21/263

CPC分类号： H01L21/28176 ,  H01L29/4908 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/6656 ,  H01L29/66575 ,  H01L29/66772 ,  H01L29/7833 ,  H01L29/78684

摘要： The present invention provides a gate stack structure that has high mobilities and low interfacial charges as well as semiconductor devices, i.e., metal oxide semiconductor field effect transistors (MOSFETs) that include the same. In the semiconductor devices, the gate stack structure of the present invention is located between the substrate and an overlaying gate conductor. The present invention also provides a method of fabricating the inventive gate stack structure in which a high temperature annealing process (on the order of about 800° C.) is employed. The high temperature anneal used in the present invention provides a gate stack structure that has an interface state density, as measured by charge pumping, of about 8×1010 charges/cm2 or less, a peak mobility of about 250 cm2V-s or greater and substantially no mobility degradation at about 6.0×1012 inversion charges/cm2 or greater.

摘要翻译： 本发明提供具有高移动性和低界面电荷的栅叠层结构，以及包括其的半导体器件，即金属氧化物半导体场效应晶体管（MOSFET）。 在半导体器件中，本发明的栅极堆叠结构位于衬底和覆盖栅极导体之间​​。 本发明还提供一种制造本发明的栅叠层结构的方法，其中采用了高温退火工艺（大约800℃）。 本发明中使用的高温退火提供了具有大约8×10 10电荷/ cm 2或更小的电荷泵浦的界面状态密度，约250cm 2 / s以上的峰值迁移率和基本上没有 约6.0×10 12反相电荷/ cm 2以上的迁移率降解。