公开(公告)号：US07186648B1

公开(公告)日：2007-03-06

申请号：US10804353

申请日：2004-03-18

申请人： Robert Rozbicki ,  Michal Danek

发明人： Robert Rozbicki ,  Michal Danek

IPC分类号： H01L21/44

CPC分类号： H01L21/76814 ,  H01L21/2855 ,  H01L21/76805 ,  H01L21/76843 ,  H01L21/76844 ,  H01L21/76865

摘要： Methods for forming a diffusion barrier on low aspect features of an integrated circuit include at least three operations. The first operation deposits a barrier material and simultaneously etches a portion of an underlying metal at the bottoms of recessed features of the integrated circuit. The second operation deposits barrier material to provide some minimal coverage over the bottoms of the recessed features. The third operation deposits a metal conductive layer. Controlled etching is used to selectively remove barrier material from the bottom of the recessed features, either completely or partially, thus reducing the resistance of subsequently formed metal interconnects.

摘要翻译： 在集成电路的低方面特征上形成扩散阻挡层的方法包括至少三个操作。 第一操作沉积阻挡材料并且同时在集成电路的凹陷特征的底部蚀刻下面的金属的一部分。 第二操作沉积阻挡材料以在凹陷特征的底部提供一些最小的覆盖。 第三操作沉积金属导电层。 使用受控蚀刻来完全或部分地从凹陷特征的底部选择性地去除阻挡材料，从而降低随后形成的金属互连的电阻。

公开(公告)号：US06764940B1

公开(公告)日：2004-07-20

申请号：US10412562

申请日：2003-04-11

申请人： Robert Rozbicki ,  Michal Danek

发明人： Robert Rozbicki ,  Michal Danek

IPC分类号： H01L214763

CPC分类号： H01L21/76843 ,  H01J37/32082 ,  H01L21/02043 ,  H01L21/76805 ,  H01L21/76807 ,  H01L21/76844 ,  H01L21/76846 ,  H01L21/7685 ,  H01L21/76862 ,  H01L21/76865 ,  H01L21/76883

摘要： Methods for forming a metal diffusion barrier on an integrated circuit include at least four operations. The first operation deposits barrier material via PVD, ALD or CVD to provide some minimal coverage. The second operation deposits an additional barrier material and simultaneously etches a portion of the barrier material deposited in the first operation. The third operation deposits barrier material via PVD, ALD or CVD to provide some minimal coverage especially over the bottoms of unlanded vias. The forth operation deposits a metal conductive layer. Controlled etching is used to selectively remove barrier material from the bottom of vias, either completely or partially, thus reducing the resistance of subsequently formed metal interconnects. In addition, techniques to protect the bottoms of the unlanded vias are described.

摘要翻译： 在集成电路上形成金属扩散阻挡层的方法包括至少四个操作。 第一个操作通过PVD，ALD或CVD沉积阻挡材料以提供一些最小的覆盖。 第二操作沉积另外的阻挡材料，同时蚀刻在第一操作中沉积的阻挡材料的一部分。 第三个操作通过PVD，ALD或CVD沉积阻挡材料，以提供一些最小的覆盖范围，特别是在非通孔的底部。 第四操作沉积金属导电层。 使用受控蚀刻来选择性地从通孔底部去除屏障材料，完全或部分地去除，从而降低随后形成的金属互连的电阻。 此外，描述了保护未经过过孔的底部的技术。

公开(公告)号：US07732314B1

公开(公告)日：2010-06-08

申请号：US11714465

申请日：2007-03-05

申请人： Michal Danek ,  Robert Rozbicki

发明人： Michal Danek ,  Robert Rozbicki

IPC分类号： H01L21/20

CPC分类号： H01L21/76814 ,  H01L21/2855 ,  H01L21/76805 ,  H01L21/76843 ,  H01L21/76844 ,  H01L21/76865

摘要： Methods for forming a metal diffusion barrier on an integrated circuit include at least four operations. The first operation deposits barrier material via PVD, ALD or CVD to provide some minimal coverage. The second operation deposits an additional barrier material and simultaneously etches a portion of the barrier material deposited in the first operation. The third operation deposits barrier material via PVD, ALD or CVD to provide some minimal coverage especially over the bottoms of unlanded vias. The forth operation deposits a metal conductive layer. Controlled etching is used to selectively remove barrier material from the bottom of vias, either completely or partially, thus reducing the resistance of subsequently formed metal interconnects. In addition, techniques to protect the bottoms of the unlanded vias are described.

摘要翻译： 在集成电路上形成金属扩散阻挡层的方法包括至少四个操作。 第一个操作通过PVD，ALD或CVD沉积阻挡材料以提供一些最小的覆盖。 第二操作沉积另外的阻挡材料，同时蚀刻在第一操作中沉积的阻挡材料的一部分。 第三个操作通过PVD，ALD或CVD沉积阻挡材料，以提供一些最小的覆盖范围，特别是在非通孔的底部。 第四操作沉积金属导电层。 使用受控蚀刻来选择性地从通孔底部去除屏障材料，完全或部分地去除，从而降低随后形成的金属互连的电阻。 此外，描述了保护未经过过孔的底部的技术。

公开(公告)号：US06642146B1

公开(公告)日：2003-11-04

申请号：US10121949

申请日：2002-04-10

申请人： Robert Rozbicki ,  Michal Danek ,  Erich Klawuhn

发明人： Robert Rozbicki ,  Michal Danek ,  Erich Klawuhn

IPC分类号： H01L2144

CPC分类号： H01L21/76843 ,  H01L21/76805 ,  H01L21/76844 ,  H01L21/76846 ,  H01L21/76862 ,  H01L21/76865

摘要： The present invention pertains to methods for depositing a metal seed layer on a wafer substrate having a plurality of recessed features. Methods of the invention include at least two operations. A first portion of a seed layer is deposited such that metal ions impinge on the wafer substrate substantially perpendicular to the wafer substrate work surface. The first portion is characterized by heavy bottom coverage in the recessed features and minimal overhang on the apertures of the recessed features. A second portion of the metal seed layer is deposited with simultaneous re-sputter of at least part of the first portion that covers the bottom of the features. During re-sputter, part of the seed material on the bottom is redistributed to the sidewalls of the features. Seed layers of the invention have minimal overhang and excellent step coverage.

摘要翻译： 本发明涉及在具有多个凹陷特征的晶片衬底上沉积金属晶种层的方法。 本发明的方法包括至少两个操作。 种子层的第一部分被沉积，使得金属离子基本上垂直于晶片衬底工作表面撞击在晶片衬底上。 第一部分的特征在于凹陷特征中的重底部覆盖和凹陷特征的孔上的最小突出。 沉积金属种子层的第二部分，同时重新溅射覆盖特征底部的第一部分的至少一部分。 在重新溅射期间，底部的种子材料的一部分重新分布到特征的侧壁。 本发明的种子层具有最小的悬垂和优异的阶梯覆盖。

公开(公告)号：US06607977B1

公开(公告)日：2003-08-19

申请号：US09965472

申请日：2001-09-26

申请人： Robert Rozbicki ,  Michal Danek ,  Erich Klawuhn

发明人： Robert Rozbicki ,  Michal Danek ,  Erich Klawuhn

IPC分类号： H01L214763

CPC分类号： H01L21/76843 ,  H01L21/76805 ,  H01L21/76844 ,  H01L21/76846 ,  H01L21/76862 ,  H01L21/76865

摘要： The present invention pertains to methods for forming a metal diffusion barrier on an integrated circuit wherein the formation includes at least two operations. The first operation deposits barrier material via PVD or CVD to provide some minimal coverage. The second operation deposits an additional barrier material and simultaneously etches a portion of the barrier material deposited in the first operation. The result of the operations is a metal diffusion barrier formed in part by net etching in certain areas, in particular the bottom of vias, and a net deposition in other areas, in particular the side walls of vias. Controlled etching is used to selectively remove barrier material from the bottom of vias, either completely or partially, thus reducing the resistance of subsequently formed metal interconnects.

摘要翻译： 本发明涉及在集成电路上形成金属扩散阻挡层的方法，其中形成包括至少两个操作。 第一个操作通过PVD或CVD沉积阻挡材料以提供一些最小的覆盖。 第二操作沉积另外的阻挡材料，同时蚀刻在第一操作中沉积的阻挡材料的一部分。 操作的结果是部分地通过在某些区域中的网蚀刻形成的金属扩散屏障，特别是通孔的底部，以及在其它区域，特别是通孔的侧壁中的净沉积。 使用受控蚀刻来选择性地从通孔底部去除屏障材料，完全或部分地去除，从而降低随后形成的金属互连的电阻。

公开(公告)号：US08685867B1

公开(公告)日：2014-04-01

申请号：US13315123

申请日：2011-12-08

申请人： Michal Danek ,  Bart van Schravendijk ,  Nerissa Draeger ,  Lakshminarayana Nittala

发明人： Michal Danek ,  Bart van Schravendijk ,  Nerissa Draeger ,  Lakshminarayana Nittala

IPC分类号： H01L21/311 ,  H01L21/00

CPC分类号： H01L21/02126 ,  H01L21/02164 ,  H01L21/02274 ,  H01L21/0234 ,  H01L21/02348 ,  H01L21/3105 ,  H01L21/76801 ,  H01L21/76814 ,  H01L21/76825 ,  H01L21/76826 ,  H01L21/76828 ,  H01L21/76837

摘要： Provided herein are novel pre-metal dielectric (PMD) integration schemes. According to various embodiments, the methods involve depositing flowable dielectric material to fill trenches or other gaps between gate structures in a front end of line (FEOL) fabrication process. The flowable dielectric material may be partially densified to form dual density filled gaps having a low density region capped by a high density region. In certain embodiments, the methods include further treating at least a portion of the gap fill material after subsequent process operations such as chemical mechanical planarization (CMP) or contact etching.

摘要翻译： 本文提供了新颖的金属前介电（PMD）集成方案。 根据各种实施例，所述方法包括沉积可流动介电材料以填充前端（FEOL）制造工艺中的栅极结构之间的沟槽或其它间隙。 可流动电介质材料可以被部分致密化以形成具有由高密度区域覆盖的低密度区域的双重密度填充间隙。 在某些实施方案中，所述方法包括在后续处理操作（例如化学机械平面化（CMP））或接触蚀刻之后进一步处理间隙填充材料的至少一部分。

公开(公告)号：US08435894B2

公开(公告)日：2013-05-07

申请号：US13351970

申请日：2012-01-17

申请人： Anand Chandrashekar ,  Raashina Humayun ,  Michal Danek ,  Aaron R. Fellis ,  Sean Chang

发明人： Anand Chandrashekar ,  Raashina Humayun ,  Michal Danek ,  Aaron R. Fellis ,  Sean Chang

IPC分类号： H01L21/44

CPC分类号： H01L21/486 ,  H01L21/28556 ,  H01L21/32136 ,  H01L21/76865 ,  H01L21/76877

摘要： Methods and apparatuses for filling high aspect ratio features with tungsten-containing materials in a substantially void-free manner are provided. In certain embodiments, the method involves depositing an initial layer of a tungsten-containing material followed by selectively removing a portion of the initial layer to form a remaining layer, which is differentially passivated along the depth of the high-aspect ration feature. In certain embodiments, the remaining layer is more passivated near the feature opening than inside the feature. The method may proceed with depositing an additional layer of the same or other material over the remaining layer. The deposition rate during this later deposition operation is slower near the feature opening than inside the features due to the differential passivation of the remaining layer. This deposition variation, in turn, may aid in preventing premature closing of the feature and facilitate filling of the feature in a substantially void free manner.

摘要翻译： 提供了以基本上无空隙的方式用含钨材料填充高纵横比特征的方法和装置。 在某些实施方案中，该方法包括沉积含钨材料的初始层，然后选择性地去除初始层的一部分以形成沿着高纵横比特征的深度差异钝化的剩余层。 在某些实施例中，剩余层在特征开口附近比在特征内更加钝化。 该方法可以继续在剩余层上沉积相同或其它材料的附加层。 由于剩余层的差分钝化，在该后续沉积操作期间的沉积速率在特征开口附近比在特征内部的沉积速率更慢。 这种沉积变化又可以有助于防止特征的过早闭合并且有助于以基本无空隙的方式填充特征。

公开(公告)号：US20120115329A1

公开(公告)日：2012-05-10

申请号：US13351970

申请日：2012-01-17

申请人： Anand Chandrashekar ,  Raashina Humayun ,  Michal Danek ,  Aaron R. Fellis ,  Sean Chang

发明人： Anand Chandrashekar ,  Raashina Humayun ,  Michal Danek ,  Aaron R. Fellis ,  Sean Chang

IPC分类号： H01L21/768

CPC分类号： H01L21/486 ,  H01L21/28556 ,  H01L21/32136 ,  H01L21/76865 ,  H01L21/76877

摘要： Methods and apparatuses for filling high aspect ratio features with tungsten-containing materials in a substantially void-free manner are provided. In certain embodiments, the method involves depositing an initial layer of a tungsten-containing material followed by selectively removing a portion of the initial layer to form a remaining layer, which is differentially passivated along the depth of the high-aspect ration feature. In certain embodiments, the remaining layer is more passivated near the feature opening than inside the feature. The method may proceed with depositing an additional layer of the same or other material over the remaining layer. The deposition rate during this later deposition operation is slower near the feature opening than inside the features due to the differential passivation of the remaining layer. This deposition variation, in turn, may aid in preventing premature closing of the feature and facilitate filling of the feature in a substantially void free manner.

摘要翻译： 提供了以基本上无空隙的方式用含钨材料填充高纵横比特征的方法和装置。 在某些实施方案中，该方法包括沉积含钨材料的初始层，然后选择性地去除初始层的一部分以形成沿着高纵横比特征的深度差异钝化的剩余层。 在某些实施例中，剩余层在特征开口附近比在特征内更加钝化。 该方法可以继续在剩余层上沉积相同或其它材料的附加层。 由于剩余层的差分钝化，在该后续沉积操作期间的沉积速率在特征开口附近比在特征内部的沉积速率更慢。 这种沉积变化又可以有助于防止特征的过早闭合并且有助于以基本无空隙的方式填充特征。

公开(公告)号：US20100267230A1

公开(公告)日：2010-10-21

申请号：US12755248

申请日：2010-04-06

申请人： Anand Chandrashekar ,  Feng Chen ,  Raashina Humayun ,  Michal Danek

发明人： Anand Chandrashekar ,  Feng Chen ,  Raashina Humayun ,  Michal Danek

IPC分类号： H01L21/768 ,  B05C11/00

CPC分类号： H01L23/535 ,  C23C16/0272 ,  C23C16/045 ,  C23C16/14 ,  C23C16/45523 ,  C23C16/52 ,  H01L21/28556 ,  H01L21/67017 ,  H01L21/76816 ,  H01L21/76843 ,  H01L21/76876 ,  H01L21/76877 ,  H01L21/76879 ,  H01L21/76895 ,  H01L23/53266 ,  H01L2924/0002 ,  H01L2924/00

摘要： Provided are methods of void-free tungsten fill of high aspect ratio features. According to various embodiments, the methods involve a reduced temperature chemical vapor deposition (CVD) process to fill the features with tungsten. In certain embodiments, the process temperature is maintained at less than about 350° C. during the chemical vapor deposition to fill the feature. The reduced-temperature CVD tungsten fill provides improved tungsten fill in high aspect ratio features, provides improved barriers to fluorine migration into underlying layers, while achieving similar thin film resistivity as standard CVD fill. Also provided are methods of depositing thin tungsten films having low-resistivity. According to various embodiments, the methods involve performing a reduced temperature low resistivity treatment on a deposited nucleation layer prior to depositing a tungsten bulk layer and/or depositing a bulk layer via a reduced temperature CVD process followed by a high temperature CVD process.

摘要翻译： 提供了高空隙特征的无空隙钨填充的方法。 根据各种实施方案，该方法包括用钨填充特征的降温化学气相沉积（CVD）工艺。 在某些实施方案中，在化学气相沉积期间将工艺温度保持在小于约350℃以填充该特征。 降低温度的CVD钨填料提供了改进的高纵横比特征的钨填充，为氟迁移到下层提供了改进的障碍，同时获得与标准CVD填充相似的薄膜电阻率。 还提供了沉积具有低电阻率的薄钨膜的方法。 根据各种实施例，所述方法包括在沉积钨体层之前对沉积的成核层进行降低温度的低电阻率处理，和/或通过降温CVD工艺沉积体层，接着进行高温CVD工艺。

公开(公告)号：US20050148209A1

公开(公告)日：2005-07-07

申请号：US10897479

申请日：2004-07-23

申请人： Karen Chu ,  Anil Vijayendran ,  Michal Danek

发明人： Karen Chu ,  Anil Vijayendran ,  Michal Danek

IPC分类号： H01L21/26 ,  H01L21/285 ,  H01L21/768 ,  H01L29/00

CPC分类号： H01L21/76843 ,  H01L21/28556 ,  H01L21/76807 ,  H01L21/76826 ,  H01L21/76831

摘要： Methods and structures are provided for conformal lining of dual damascene structures in semiconductor devices that contain porous or low k dielectrics. Features, such as trenches and contact vias are formed in the dielectrics. The features are subjected to low-power plasma predeposition treatment to irregularities on the porous surfaces and/or reactively form an permeation barrier before a diffusion barrier material is deposited on the feature. The diffusion barrier may, for example, be deposited by CVD using metalorganic vapor reagents. The feature is then filled with copper metal and further processed to complete a dual damascene interconnect. The plasma predeposition treatment advantageously reduces the amount of permeation of the metalorganic reagent into the interlayer dielectric.

摘要翻译： 为包含多孔或低k电介质的半导体器件中的双镶嵌结构的保形衬里提供了方法和结构。 在电介质中形成诸如沟槽和接触通孔的特征。 这些特征经受低功率等离子体预沉积处理到多孔表面上的不规则性和/或在扩散阻挡材料沉积在特征上之前反应形成渗透屏障。 可以使用金属有机蒸汽试剂通过CVD沉积扩散阻挡层。 该特征然后用铜金属填充并进一步处理以完成双镶嵌互连。 等离子体预沉积处理有利地减少了金属有机试剂渗透到层间电介质中的量。