公开(公告)号：US20220415855A1

公开(公告)日：2022-12-29

申请号：US17682773

申请日：2022-02-28

Applicant: Micron Technology, Inc.

Inventor： Brent Keeth ,  Mark Hiatt ,  Terry R. Lee ,  Mark Tuttle ,  Rahul Advani ,  John F. Schreck

IPC: H01L25/065 ,  H01L23/50 ,  H01L23/66

Abstract: Some embodiments include apparatus, systems, and methods having a base, a first die, a second arranged in a stacked with the first die and the base, and a structure located in the stack and outside at least one of the first and second dice and configured to transfer signals between the base and at least one of the first and second dice.

公开(公告)号：US10468382B2

公开(公告)日：2019-11-05

申请号：US15137931

申请日：2016-04-25

Applicant: Micron Technology, Inc.

Inventor： Brent Keeth ,  Mark Hiatt ,  Terry R. Lee ,  Mark Tuttle ,  Rahul Advani ,  John F. Schreck

IPC: B23P19/00 ,  H01L25/065 ,  H01L23/50 ,  H01L23/66 ,  H01L23/538

Abstract: Some embodiments include apparatus, systems, and methods having a base, a first die, a second arranged in a stacked with the first die and the base, and a structure located in the stack and outside at least one of the first and second dice and configured to transfer signals between the base and at least one of the first and second dice.

公开(公告)号：US09019779B2

公开(公告)日：2015-04-28

申请号：US14046756

申请日：2013-10-04

Applicant: Micron Technology, Inc.

Inventor： Terry R. Lee ,  Joseph Jeddeloh

IPC: G11C7/10 ,  G11C5/02 ,  H05K1/18 ,  H05K1/02

CPC classification number: G11C5/02 ,  H05K1/0298 ,  H05K1/181 ,  H05K2201/09972 ,  Y02P70/611

Abstract: A layout for simultaneously sub-accessible memory modules is disclosed. In one embodiment, a memory module includes a printed circuit board having a plurality of sectors, each sector being electrically isolated from the other sectors and having a multi-layer structure. At least one memory device is attached to each sector, the memory devices being organized into a plurality of memory ranks. A driver is attached to the printed circuit board and is operatively coupled to the memory ranks. The driver is adapted to be coupled to a memory interface of the computer system. Because the sectors are electrically-isolated from adjacent sectors, the memory ranks are either individually or simultaneously, or both individually and simultaneously accessible by the driver so that one or more memory devices on a particular sector may be accessed at one time. In an alternate embodiment, the printed circuit board includes a driver sector electrically isolated from the other sectors and having a multi-layer structure, the driver being attached to the driver sector.

Abstract translation: 公开了一种用于同时可辅助存储器模块的布局。 在一个实施例中，存储器模块包括具有多个扇区的印刷电路板，每个扇区与其它扇区电隔离并且具有多层结构。 至少一个存储器装置连接到每个扇区，存储器装置被组织成多个存储器等级。 驱动器连接到印刷电路板并且可操作地耦合到存储器等级。 驱动器适于耦合到计算机系统的存储器接口。 由于扇区与相邻扇区电隔离，所以存储器排列是单独地或同时地存在的，或者由驱动器单独地并且可以同时访问，使得一次可以访问特定扇区上的一个或多个存储器件。 在替代实施例中，印刷电路板包括与其他扇区电隔离并具有多层结构的驱动器扇区，该驱动器附接到驱动器扇区。

公开(公告)号：US20140029325A1

公开(公告)日：2014-01-30

申请号：US14046756

申请日：2013-10-04

Applicant: Micron Technology, Inc.

Inventor： Terry R. Lee ,  Joseph Jeddeloh

IPC: G11C5/02

CPC classification number: G11C5/02 ,  H05K1/0298 ,  H05K1/181 ,  H05K2201/09972 ,  Y02P70/611

Abstract: A layout for simultaneously sub-accessible memory modules is disclosed. In one embodiment, a memory module includes a printed circuit board having a plurality of sectors, each sector being electrically isolated from the other sectors and having a multi-layer structure. At least one memory device is attached to each sector, the memory devices being organized into a plurality of memory ranks. A driver is attached to the printed circuit board and is operatively coupled to the memory ranks. The driver is adapted to be coupled to a memory interface of the computer system. Because the sectors are electrically-isolated from adjacent sectors, the memory ranks are either individually or simultaneously, or both individually and simultaneously accessible by the driver so that one or more memory devices on a particular sector may be accessed at one time. In an alternate embodiment, the printed circuit board includes a driver sector electrically isolated from the other sectors and having a multi-layer structure, the driver being attached to the driver sector.

Abstract translation: 公开了一种用于同时可辅助存储器模块的布局。 在一个实施例中，存储器模块包括具有多个扇区的印刷电路板，每个扇区与其它扇区电隔离并且具有多层结构。 至少一个存储器装置连接到每个扇区，存储器装置被组织成多个存储器等级。 驱动器连接到印刷电路板并且可操作地耦合到存储器等级。 驱动器适于耦合到计算机系统的存储器接口。 由于扇区与相邻扇区电隔离，所以存储器排列是单独地或同时地存在的，或者由驱动器单独地并且可以同时访问，使得一次可以访问特定扇区上的一个或多个存储器件。 在替代实施例中，印刷电路板包括与其他扇区电隔离并具有多层结构的驱动器扇区，该驱动器附接到驱动器扇区。

公开(公告)号：US11264360B2

公开(公告)日：2022-03-01

申请号：US16665923

申请日：2019-10-28

Applicant: Micron Technology, Inc.

Inventor： Brent Keeth ,  Mark Hiatt ,  Terry R. Lee ,  Mark Tuttle ,  Rahul Advani ,  John F. Schreck

IPC: H05K3/02 ,  H01L25/065 ,  H01L23/50 ,  H01L23/66 ,  H01L23/538

Abstract: Some embodiments include apparatus, systems, and methods having a base, a first die, a second arranged in a stacked with the first die and the base, and a structure located in the stack and outside at least one of the first and second dice and configured to transfer signals between the base and at least one of the first and second dice.

公开(公告)号：US20200058621A1

公开(公告)日：2020-02-20

申请号：US16665923

申请日：2019-10-28

Applicant: Micron Technology, Inc.

Inventor： Brent Keeth ,  Mark Hiatt ,  Terry R. Lee ,  Mark Tuttle ,  Rahul Advani ,  John F. Schreck

IPC: H01L25/065 ,  H01L23/66 ,  H01L23/50

Abstract: Some embodiments include apparatus, systems, and methods having a base, a first die, a second arranged in a stacked with the first die and the base, and a structure located in the stack and outside at least one of the first and second dice and configured to transfer signals between the base and at least one of the first and second dice.

公开(公告)号：US20160240515A1

公开(公告)日：2016-08-18

申请号：US15137931

申请日：2016-04-25

Applicant: Micron Technology, Inc.

Inventor： Brent Keeth ,  Mark Hiatt ,  Terry R. Lee ,  Mark Tuttle ,  Rahul Advani ,  John F. Schreck

IPC: H01L25/065 ,  H01L23/66 ,  H01L23/50

CPC classification number: H01L25/0657 ,  H01L23/50 ,  H01L23/5385 ,  H01L23/66 ,  H01L25/0655 ,  H01L2223/6677 ,  H01L2224/0401 ,  H01L2224/06181 ,  H01L2224/14181 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/17181 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/0652 ,  H01L2225/06541 ,  H01L2225/06572 ,  H01L2924/01004 ,  H01L2924/15192 ,  H01L2924/15311 ,  Y10T29/49165 ,  Y10T29/5317

Abstract: Some embodiments include apparatus, systems, and methods having a base, a first die, a second arranged in a stacked with the first die and the base, and a structure located in the stack and outside at least one of the first and second dice and configured to transfer signals between the base and at least one of the first and second dice.