公开(公告)号：US07852412B1

公开(公告)日：2010-12-14

申请号：US11363627

申请日：2006-02-27

申请人： Miguel A. Guerrero ,  Stephen D. Lew ,  Gerrit A. Slavenburg

发明人： Miguel A. Guerrero ,  Stephen D. Lew ,  Gerrit A. Slavenburg

IPC分类号： H04N5/21 ,  H04N5/213 ,  H04N5/14

CPC分类号： H04N5/21 ,  G06T5/002 ,  G06T5/003 ,  G06T5/20 ,  G06T7/0002 ,  G06T2207/10016 ,  G06T2207/20182 ,  G06T2207/20192 ,  H04N17/00

摘要： Circuits, methods, and apparatus for measuring a video signal's noise level. The determination can be made based on pixel values for a single video image frame, for example, by comparing pixel color values, luminance, or other parameter for a first and second group of pixels in the frame. Each group of pixels may be part of a line in the frame, and several such measurements may be made along each line of the frame. These measurements can then be further refined depending on the measure noise level. Once a video noise level is determined, a decision on how to further process the video signal can be made. For example, the picture can be filtered or sharpened. The amount of noise filtering can be made dependent on the amount of noise measured.

摘要翻译： 用于测量视频信号噪声电平的电路，方法和装置。 可以基于单个视频图像帧的像素值进行确定，例如通过比较帧中的第一和第二像素组的像素颜色值，亮度或其他参数。 每组像素可以是帧中的线的一部分，并且可以沿着帧的每一行进行若干这样的测量。 然后可以根据测量噪声水平进一步改进这些测量。 一旦确定了视频噪声电平，就可以做出关于如何进一步处理视频信号的决定。 例如，可以对图片进行过滤或锐化。 噪声滤波的量可以取决于测量的噪声量。

公开(公告)号：US20140055559A1

公开(公告)日：2014-02-27

申请号：US13568875

申请日：2012-08-07

申请人： Jen-Hsun Huang ,  Gerrit A. Slavenburg ,  Stephen D. Lew ,  John C. Schafer ,  Thomas F. Fox ,  Taner E. Ozcelik

发明人： Jen-Hsun Huang ,  Gerrit A. Slavenburg ,  Stephen D. Lew ,  John C. Schafer ,  Thomas F. Fox ,  Taner E. Ozcelik

IPC分类号： G06T15/00 ,  H04N13/00

CPC分类号： G06T15/005 ,  G06F15/78 ,  G09G5/003 ,  G09G2360/02 ,  H04N13/161

摘要： Circuits, methods, and apparatus that provide highly integrated digital media processors for digital consumer electronics applications. These digital media processors are capable of performing the parallel processing of multiple format audio, video, and graphics signals. In one embodiment, audio and video signals may be received from a variety of input devices or appliances, such as antennas, VCRs, DVDs, and networked devices such as camcorders and modems, while output audio and video signals may be provided to output devices such as televisions, monitors, and networked devices such as printers and networked video recorders. Another embodiment of the present invention interfaces with a variety of devices such as navigation, entertainment, safety, memory, and networking devices. This embodiment can also be configured for use in a digital TV, set-top box, or home server. In this configuration, video and audio streams may be received from a number of cable, satellite, Internet, and consumer devices.

摘要翻译： 为数字消费电子应用提供高度集成的数字媒体处理器的电路，方法和设备。 这些数字媒体处理器能够执行多格式音频，视频和图形信号的并行处理。 在一个实施例中，音频和视频信号可以从诸如天线，VCR，DVD以及诸如摄像机和调制解调器之类的网络设备的各种输入设备或设备接收，而输出音频和视频信号可以被提供给诸如 作为电视机，显示器和网络设备，如打印机和网络录像机。 本发明的另一实施例与诸如导航，娱乐，安全，存储器和网络设备的各种设备接口。 该实施例还可以被配置为用于数字电视，机顶盒或家庭服务器中。 在该配置中，可以从多个有线，卫星，因特网和消费者设备接收视频和音频流。

公开(公告)号：US08253750B1

公开(公告)日：2012-08-28

申请号：US12832830

申请日：2010-07-08

申请人： Jen-Hsun Huang ,  Gerrit A. Slavenburg ,  Stephen D. Lew ,  John C. Schafer ,  Thomas F. Fox ,  Taner E. Ozcelik

发明人： Jen-Hsun Huang ,  Gerrit A. Slavenburg ,  Stephen D. Lew ,  John C. Schafer ,  Thomas F. Fox ,  Taner E. Ozcelik

IPC分类号： G06F13/14 ,  G06F15/80 ,  G06F15/00

CPC分类号： G06T15/005 ,  G06F15/78 ,  G09G5/003 ,  G09G2360/02 ,  H04N13/161

摘要： Circuits, methods, and apparatus that provide highly integrated digital media processors for digital consumer electronics applications. These digital media processors are capable of performing the parallel processing of multiple format audio, video, and graphics signals. In one embodiment, audio and video signals may be received from a variety of input devices or appliances, such as antennas, VCRs, DVDs, and networked devices such as camcorders and modems, while output audio and video signals may be provided to output devices such as televisions, monitors, and networked devices such as printers and networked video recorders. Another embodiment of the present invention interfaces with a variety of devices such as navigation, entertainment, safety, memory, and networking devices. This embodiment can also be configured for use in a digital TV, set-top box, or home server. In this configuration, video and audio streams may be received from a number of cable, satellite, Internet, and consumer devices.

摘要翻译： 为数字消费电子应用提供高度集成的数字媒体处理器的电路，方法和设备。 这些数字媒体处理器能够执行多格式音频，视频和图形信号的并行处理。 在一个实施例中，音频和视频信号可以从诸如天线，VCR，DVD以及诸如摄像机和调制解调器之类的网络设备的各种输入设备或设备接收，而输出音频和视频信号可以被提供给诸如 作为电视机，显示器和网络设备，如打印机和网络录像机。 本发明的另一实施例与诸如导航，娱乐，安全，存储器和网络设备的各种设备接口。 该实施例还可以被配置为用于数字电视，机顶盒或家庭服务器中。 在该配置中，可以从多个有线，卫星，因特网和消费者设备接收视频和音频流。

公开(公告)号：US07624224B1

公开(公告)日：2009-11-24

申请号：US11301650

申请日：2005-12-13

申请人： Shang-Tse Chuang ,  Stephen D. Lew ,  Gerrit A. Slavenburg

发明人： Shang-Tse Chuang ,  Stephen D. Lew ,  Gerrit A. Slavenburg

IPC分类号： G06F12/00

CPC分类号： G06F12/0875 ,  G06F9/44505 ,  G06F2212/2022

摘要： A system, method, and computer program product are provided for directly executing code in block-based memory, which resides in communication with a processor and a controller. Utilizing the controller, a request is received from the processor for a subset of a block of data in the block-based memory, and at least a portion of the block is retrieved from the block-based memory. After the retrieval, at least a portion of the block is stored in a cache. The subset of the block is then transmitted to the processor, utilizing the controller. To this end, code in the block-based memory is directly executed.

摘要翻译： 提供了一种用于在基于块的存储器中直接执行代码的系统，方法和计算机程序产品，其驻留在与处理器和控制器的通信中。 利用控制器，从处理器接收基于块的存储器中的数据块的子集的请求，并且从基于块的存储器检索块的至少一部分。 在检索之后，块的至少一部分被存储在高速缓存中。 然后利用控制器将块的子集发送到处理器。 为此，直接执行基于块的内存中的代码。

公开(公告)号：US08203562B1

公开(公告)日：2012-06-19

申请号：US12243766

申请日：2008-10-01

申请人： Jonah M. Alben ,  Stephen D. Lew ,  Paolo E. Sabella

发明人： Jonah M. Alben ,  Stephen D. Lew ,  Paolo E. Sabella

IPC分类号： G06T15/00 ,  G06F15/16

CPC分类号： G06F15/16 ,  G06F9/5044 ,  G06T1/20 ,  G06T15/005 ,  G09G5/363 ,  G09G2330/021 ,  G09G2360/06 ,  Y02D10/22

摘要： An integrated circuit includes at least two different types of processors, such as a graphics processor and a video processor. At least one operation is commonly by supported by two different types of processors. For each commonly supported operation that is scheduled, a decision is made to determine which type of processor will be selected to implement the operation.

摘要翻译： 集成电路包括至少两种不同类型的处理器，诸如图形处理器和视频处理器。 通常由两种不同类型的处理器支持至少一种操作。 对于被调度的每个通常支持的操作，作出决定以确定将选择哪种类型的处理器来实现该操作。

公开(公告)号：US20110238955A1

公开(公告)日：2011-09-29

申请号：US13099035

申请日：2011-05-02

申请人： John R. Nickolls ,  Stephen D. Lew

发明人： John R. Nickolls ,  Stephen D. Lew

IPC分类号： G06F9/30

CPC分类号： G06F9/3851 ,  G06F9/30072 ,  G06F9/3012 ,  G06F9/3889 ,  G06F9/5066

摘要： Parallelism in a parallel processing subsystem is exploited in a scalable manner. A problem to be solved can be hierarchically decomposed into at least two levels of sub-problems. Individual threads of program execution are defined to solve the lowest-level sub-problems. The threads are grouped into one or more thread arrays, each of which solves a higher-level sub-problem. The thread arrays are executable by processing cores, each of which can execute at least one thread array at a time. Thread arrays can be grouped into grids of independent thread arrays, which solve still higher-level sub-problems or an entire problem. Thread arrays within a grid, or entire grids, can be distributed across all of the available processing cores as available in a particular system implementation.

摘要翻译： 并行处理子系统中的并行性以可扩展的方式被利用。 要解决的问题可以被分层分解成至少两个级别的子问题。 定义程序执行的各个线程来解决最低级别的问题。 线程被分组成一个或多个线程数组，每个线程数组都解决了较高级的子问题。 线程数组可以通过处理内核执行，每个核心可以一次执行至少一个线程数组。 线程数组可以分组成独立线程数组的网格，从而解决更高级的子问题或整个问题。 网格中的线程数组或整个网格可以分布在所有可用处理核心中，如特定系统实现中可用的。

公开(公告)号：US07876378B1

公开(公告)日：2011-01-25

申请号：US11957361

申请日：2007-12-14

申请人： Stephen D. Lew ,  Garry W. Amann ,  Hassane S. Azar

发明人： Stephen D. Lew ,  Garry W. Amann ,  Hassane S. Azar

IPC分类号： H04N5/917

CPC分类号： H04N19/86 ,  H04N7/01 ,  H04N7/012

摘要： Video filtering using a programmable graphics processor is described. The programmable graphics processor may be programmed to complete a plurality of video filtering operations in a single pass through a fragment-processing pipeline within the programmable graphics processor. Video filtering functions such as deinterlacing, chroma up-sampling, scaling, and deblocking may be performed by the fragment-processing pipeline. The fragment-processing pipeline may be programmed to perform motion adaptive deinterlacing, wherein a spatially variant filter determines, on a pixel basis, whether a “bob”, a “blend”, or a “weave” operation should be used to process an interlaced image.

摘要翻译： 描述使用可编程图形处理器的视频滤波。 可编程图形处理器可以被编程为在可编程图形处理器内的片段处理流水线的单次传递中完成多个视频滤波操作。 诸如去隔行，色度上采样，缩放和去块之类的视频滤波功能可以由片段处理流水线执行。 片段处理流水线可以被编程为执行运动自适应去隔行，其中空间变异滤波器基于像素确定是否应当使用“bob”，“blend”或“weave”操作来处理隔行扫描 图片。

公开(公告)号：US07861060B1

公开(公告)日：2010-12-28

申请号：US11305178

申请日：2005-12-15

申请人： John R. Nickolls ,  Stephen D. Lew

发明人： John R. Nickolls ,  Stephen D. Lew

IPC分类号： G06F15/16

CPC分类号： G06F9/544 ,  G06F9/3851 ,  G06F9/3887 ,  G06F9/522

摘要： Parallel data processing systems and methods use cooperative thread arrays (CTAs), i.e., groups of multiple threads that concurrently execute the same program on an input data set to produce an output data set. Each thread in a CTA has a unique identifier (thread ID) that can be assigned at thread launch time. The thread ID controls various aspects of the thread's processing behavior such as the portion of the input data set to be processed by each thread, the portion of an output data set to be produced by each thread, and/or sharing of intermediate results among threads. Mechanisms for loading and launching CTAs in a representative processing core and for synchronizing threads within a CTA are also described.

摘要翻译： 并行数据处理系统和方法使用协同线程数组（CIA），即在输入数据集上同时执行相同程序的多线程组，以产生输出数据集。 CTA中的每个线程都有一个唯一的标识符（线程ID），可以在线程启动时分配。 线程ID控制线程的处理行为的各个方面，例如由每个线程处理的输入数据集的部分，由每个线程产生的输出数据集的部分和/或线程之间的中间结果的共享 。 还描述了在代表性处理核心中加载和启动CTA并在CTA内同步线程的机制。

公开(公告)号：US07779191B2

公开(公告)日：2010-08-17

申请号：US12182074

申请日：2008-07-29

申请人： Chien-Ping Lu ,  Stephen D. Lew ,  Robert William Chapman

发明人： Chien-Ping Lu ,  Stephen D. Lew ,  Robert William Chapman

IPC分类号： G06F9/48

CPC分类号： G06F1/3203

摘要： A system and method for transitions a computing system between operating modes that have different power consumption characteristics. When a system management unit (SMU) determines that the computing system is in a low activity state, the SMU transitions the central processing unit (CPU) into a low power operating mode after the CPU stores critical operating state of the CPU in a memory. The SMU then intercepts and processes interrupts intended for the CPU, modifying a copy of the critical operating state. This effectively extends the time during which the CPU stays in lower power mode. When the SMU determines that the computing system exits a low activity state, the copy of the critical operating state is stored in the memory and the SMU transitions the CPU into a high power operating mode using the modified critical operating state.

摘要翻译： 一种用于在具有不同功耗特性的操作模式之间转换计算系统的系统和方法。 当系统管理单元（SMU）确定计算系统处于低活动状态时，在CPU将CPU的临界操作状态存储在存储器中之后，SMU将中央处理单元（CPU）转换为低功耗操作模式。 然后，SMU拦截并处理用于CPU的中断，修改关键操作状态的副本。 这有效地延长了CPU处于较低功耗模式的时间。 当SMU确定计算系统退出低活动状态时，关键操作状态的副本存储在存储器中，并且SMU使用修改的关键操作状态将CPU转换为高功率​​操作模式。

公开(公告)号：US07898545B1

公开(公告)日：2011-03-01

申请号：US11012464

申请日：2004-12-14

申请人： Jonah M. Alben ,  Stephen D. Lew ,  Paolo E. Sabella

发明人： Jonah M. Alben ,  Stephen D. Lew ,  Paolo E. Sabella

IPC分类号： G06F13/14 ,  G06F15/16

CPC分类号： G06F9/5094 ,  G06F9/5044 ,  Y02D10/22

摘要： An integrated circuit includes at least two different types of processors. At least one operation is supported by both types of processors, which permits a commonly supported operation to be scheduled on either processor.

摘要翻译： 集成电路包括至少两种不同类型的处理器。 两种类型的处理器支持至少一种操作，这允许在任一处理器上调度通常支持的操作。