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    Trenched DMOS transistor fabrication having thick termination region oxide
    6.
    发明授权
    Trenched DMOS transistor fabrication having thick termination region oxide 失效
    具有厚终止区氧化物的沟槽DMOS晶体管制造

    公开(公告)号：US5639676A

    公开(公告)日：1997-06-17

    申请号：US603047

    申请日：1996-02-16

    申请人： Fwu-Iuan Hshieh ,  Mike F. Chang ,  Yueh-Se Ho ,  King Owyang

    发明人： Fwu-Iuan Hshieh ,  Mike F. Chang ,  Yueh-Se Ho ,  King Owyang

    IPC分类号： H01L21/316 ,  H01L21/336 ,  H01L29/06 ,  H01L29/40 ,  H01L29/78 ,  H01L21/265 ,  H01L21/44 ,  H01L21/48

    CPC分类号： H01L29/407 ,  H01L29/404 ,  H01L29/7813

    摘要： A trenched DMOS transistor is fabricated using seven masking steps. One masking step defines both the P+ deep body regions and the active portions of the transistor which are masked using a LOCOS process. A second masking step defines the insulating oxide in the termination region. The insulating (oxide) layer in the termination region is thus thicker than in the active region of the transistor, thereby improving process control and reducing substrate contamination during processing. Additionally, the thicker field oxide in the termination region improves electric field distribution so that avalanche breakdown occurs in the cell (active) region rather than in the termination region, and thus breakdown voltage behavior is more stable and predictable.

    摘要翻译： 使用七个掩模步骤制造出沟槽的DMOS晶体管。 一个掩模步骤限定使用LOCOS工艺掩蔽的P +深体区域和晶体管的有源部分。 第二掩蔽步骤限定了端接区域中的绝缘氧化物。 因此，端接区域中的绝缘（氧化物）层比晶体管的有源区域厚，从而改善了处理过程中的工艺控制和减少了衬底污染。 此外，端接区域中较厚的场氧化物改善了电场分布，使得雪崩击穿发生在电池（有源）区而不是终端区，因此击穿电压行为更稳定和可预测。

    Surface mount and flip chip technology with diamond film passivation for total integated circuit isolation
    7.
    发明授权
    Surface mount and flip chip technology with diamond film passivation for total integated circuit isolation 失效
    表面贴装和倒装芯片技术，具有金刚石膜钝化功能，可完全集成电路隔离

    公开(公告)号：US5767578A

    公开(公告)日：1998-06-16

    申请号：US634957

    申请日：1996-04-19

    申请人： Mike F. Chang ,  King Owyang ,  Fwu-Iuan Hshieh ,  Yueh-Se Ho ,  Jowei Dun ,  Hans-Jurgen Fusser ,  Reinhard Zachai

    发明人： Mike F. Chang ,  King Owyang ,  Fwu-Iuan Hshieh ,  Yueh-Se Ho ,  Jowei Dun ,  Hans-Jurgen Fusser ,  Reinhard Zachai

    IPC分类号： H01L23/29 ,  H01L23/367 ,  H01L23/373 ,  H01L23/34

    CPC分类号： H01L23/3672 ,  H01L23/29 ,  H01L23/3732 ,  H01L2224/16 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/14

    摘要： An integrated circuit chip has full trench dielectric isolation of each portion of the chip. Initially the chip substrate is of conventional thickness and has semiconductor devices formed in it. After etching trenches in the substrate and filling them with dielectric material, a heat sink cap is attached to the passivation layer on the substrate front side surface. The passivation layer is a CVD diamond film which provides both electrical insulation and thermal conductivity. The substrate backside surface is removed (by grinding and/or CMP) to expose the bottom portion of the trenches. This fully isolates each portion of the die and eliminates mechanical stresses at the trench bottoms. Thereafter drain or collector electrical contacts are provided on the substrate backside surface. In a flip chip version, frontside electrical contacts extend through the frontside passivation layer to the heat sink cap. In a surface mount version, vias are etched through the substrate, with surface mount posts formed on the vias, to contact the frontside electrical contacts and provide all electrical contacts on the substrate backside surface. The wafer is then scribed into die in both versions without need for further packaging.

    摘要翻译： 集成电路芯片具有芯片每个部分的全沟槽绝缘隔离。 最初，芯片基板具有常规的厚度并且在其中形成半导体器件。 在蚀刻衬底中的沟槽并用电介质材料填充沟槽之后，将散热器盖附着到衬底前侧表面上的钝化层。 钝化层是提供电绝缘和导热性的CVD金刚石膜。 去除衬底背面（通过研磨和/或CMP）以暴露沟槽的底部。 这完全隔离了模具的每个部分，并消除了沟槽底部的机械应力。 此后，漏极或集电极电触点设置在基板背面上。 在倒装芯片版本中，前端电触点延伸穿过前侧钝化层到散热器盖。 在表面安装型式中，通孔穿过衬底被蚀刻，表面安装柱形成在通孔上，以接触前侧电触点并提供衬底背面上的所有电触头。 然后将晶片以两种版本刻成模具，而不需要进一步的包装。

    Surface mount and flip chip technology for total integrated circuit isolation
    8.
    发明授权
    Surface mount and flip chip technology for total integrated circuit isolation 失效
    表面贴装和倒装芯片技术，用于全集成电路隔离

    公开(公告)号：US5757081A

    公开(公告)日：1998-05-26

    申请号：US603512

    申请日：1996-02-20

    申请人： Mike F. Chang ,  King Owyang ,  Fwu-Iuan Hshieh ,  Yueh-Se Ho ,  Jowei Dun

    发明人： Mike F. Chang ,  King Owyang ,  Fwu-Iuan Hshieh ,  Yueh-Se Ho ,  Jowei Dun

    IPC分类号： H01L23/367 ,  H01L23/373 ,  H01L23/48

    CPC分类号： H01L23/3672 ,  H01L23/3738 ,  H01L2224/16 ,  H01L2224/73253 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/14 ,  Y10S148/135 ,  Y10S438/928 ,  Y10S438/977

    摘要： An integrated circuit chip has full trench dielectric isolation of each portion of the chip. Initially the chip substrate is of conventional thickness and has semiconductor devices formed in it. After etching trenches in the substrate and filling them with dielectric material, a heat sink cap is attached to the passivation layer on the substrate front side surface. The substrate backside surface is removed (by grinding or CMP) to expose the bottom portion of the trenches. This fully isolates each portion of the die and eliminates mechanical stresses at the trench bottoms. Thereafter drain or collector electrical contacts are provided on the substrate backside surface. In a flip chip version, frontside electrical contacts extend through the frontside passivation layer to the heat sink cap. In a surface mount version, vias are etched through the substrate, with surface mount posts formed on the vias, to contact the frontside electrical contacts and provide all electrical contacts on the substrate backside surface. The wafer is then scribed into die in both versions without need for further packaging.

    摘要翻译： 集成电路芯片具有芯片每个部分的全沟槽绝缘隔离。 最初，芯片基板具有常规的厚度并且在其中形成半导体器件。 在蚀刻衬底中的沟槽并用电介质材料填充沟槽之后，将散热器盖附着到衬底前侧表面上的钝化层。 通过研磨或CMP去除衬底背面以露出沟槽的底部。 这完全隔离了模具的每个部分，并消除了沟槽底部的机械应力。 此后，漏极或集电极电触点设置在基板背面上。 在倒装芯片版本中，前端电触点延伸穿过前侧钝化层到散热器盖。 在表面安装型式中，通孔穿过衬底被蚀刻，表面安装柱形成在通孔上，以接触前侧电触点并提供衬底背面上的所有电触头。 然后将晶片刻成两个版本的模具，无需进一步包装。

    Trenched DMOS transistor with channel block at cell trench corners
    10.
    发明授权
    Trenched DMOS transistor with channel block at cell trench corners 失效
    沟槽DMOS晶体管，沟槽块在沟槽角处

    公开(公告)号：US5468982A

    公开(公告)日：1995-11-21

    申请号：US253527

    申请日：1994-06-03

    申请人： Fwu-Iuan Hshieh ,  Sze-Hon Kwan ,  Mike F. Chang ,  Yueh-Se Ho ,  Jan Van Der Linde ,  King Owyang

    发明人： Fwu-Iuan Hshieh ,  Sze-Hon Kwan ,  Mike F. Chang ,  Yueh-Se Ho ,  Jan Van Der Linde ,  King Owyang

    IPC分类号： H01L21/76 ,  H01L21/336 ,  H01L29/06 ,  H01L29/40 ,  H01L29/78 ,  H01L29/68 ,  H01L21/265

    CPC分类号： H01L29/407 ,  H01L29/0696 ,  H01L29/402 ,  H01L29/7811 ,  H01L29/7813 ,  H01L29/1095 ,  H01L29/4236

    摘要： A trenched DMOS transistor has improved device performance and production yield. During fabrication the cell trench corners, i.e. the areas where two trenches intersect, are covered on the principal surface of the integrated circuit substrate with a blocking photoresist layer during the source region implant step in order to prevent (block) a channel from forming in these corner areas. Punch-through is thereby eliminated and reliability improved, while source/drain on-resistance is only slightly increased. The blocking of the trench corners creates a cutout structure at each trench corner, whereby the source region does not extend to the trench corner, but instead the underlying oppositely-doped body region extends to the trench corner.

    摘要翻译： 沟槽的DMOS晶体管具有改进的器件性能和生产产量。 在制造期间，在源区域注入步骤期间，单元沟槽角部，即两个沟槽相交的区域被覆盖在集成电路基板的主表面上，并具有阻挡光致抗蚀剂层，以便防止（阻挡）在这些区域中形成沟道 角落地区。 因此消除了穿通，并提高了可靠性，同时源极/漏极导通电阻仅略微增加。 沟槽拐角的阻塞在每个沟槽角处产生切口结构，由此源极区域不延伸到沟槽角部，而是相反地，下面相对掺杂的体区域延伸到沟槽角部。