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1.
公开(公告)号:US20110212403A1
公开(公告)日:2011-09-01
申请号:US12713335
申请日:2010-02-26
申请人: Ming-Jhih Kuo , Chun-Kuang Chen , Ya Hui Chang , Tommy Kuo , Hsien-Cheng Wang , Ko-Bin Kao
发明人: Ming-Jhih Kuo , Chun-Kuang Chen , Ya Hui Chang , Tommy Kuo , Hsien-Cheng Wang , Ko-Bin Kao
CPC分类号: G03B27/54 , G03F7/70108
摘要: Provided is a lithography system that includes a source for providing energy, an imaging system configured to direct the energy onto a substrate to form an image thereon, and a diffractive optical element (DOE) incorporated with the imaging system, the DOE having a first dipole located in a first direction and a second dipole located in the first direction or a second direction perpendicular the first direction. The first dipole includes a first energy-transmitting region spaced a first distance from a center of the DOE. The second dipole includes a second energy-transmitting region spaced a second distance from the center of the DOE. The first distance is greater than the second distance.
摘要翻译: 提供了一种包括用于提供能量的源的光刻系统,被配置为将能量引导到衬底上以在其上形成图像的成像系统,以及结合有成像系统的衍射光学元件(DOE),DOE具有第一偶极子 位于第一方向上,第二偶极位于第一方向或垂直于第一方向的第二方向。 第一偶极子包括与DOE的中心间隔开第一距离的第一能量传输区域。 第二偶极子包括与DOE的中心隔开第二距离的第二能量传输区域。 第一距离大于第二距离。
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公开(公告)号:US09543406B2
公开(公告)日:2017-01-10
申请号:US13293650
申请日:2011-11-10
CPC分类号: H01L22/32 , G03F7/70633 , H01L21/265 , H01L29/517 , H01L29/66545
摘要: The overlay mark and method for making the same are described. In one embodiment, a semiconductor overlay structure includes gate stack structures formed on the semiconductor substrate and configured as an overlay mark, and a doped semiconductor substrate disposed on both sides of the gate stack structure that includes at least as much dopant as the semiconductor substrate adjacent to the gate stack structure in a device region. The doped semiconductor substrate is formed by at least three ion implantation steps.
摘要翻译: 对覆盖标记及其制作方法进行说明。 在一个实施例中,半导体覆盖结构包括形成在半导体衬底上并被配置为覆盖标记的栅极叠层结构,以及设置在栅叠层结构两侧的掺杂半导体衬底,其至少包括与半导体衬底相邻的掺杂剂 到设备区域中的栅极堆栈结构。 掺杂半导体衬底通过至少三个离子注入步骤形成。
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公开(公告)号:US09000525B2
公开(公告)日:2015-04-07
申请号:US12783200
申请日:2010-05-19
IPC分类号: H01L21/70 , H01L21/8234 , H01L29/66
CPC分类号: H01L27/088 , H01L21/823418 , H01L21/823456 , H01L21/823493 , H01L29/4916 , H01L29/51 , H01L29/66545 , H01L29/66575 , H01L29/6659
摘要: The alignment mark and method for making the same are described. In one embodiment, a semiconductor structure includes a plurality of gate stacks formed on the semiconductor substrate and configured as an alignment mark; doped features formed in the semiconductor substrate and disposed on sides of each of the plurality of gate stacks; and channel regions underlying the plurality of gate stacks and free of channel dopant.
摘要翻译: 对准标记及其制作方法进行说明。 在一个实施例中,半导体结构包括形成在半导体衬底上并被配置为对准标记的多个栅极叠层; 掺杂特征形成在所述半导体衬底中并且设置在所述多个栅极堆叠中的每一个的侧面上; 以及在多个栅极堆叠下面并且没有沟道掺杂剂的沟道区域。
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公开(公告)号:US20110284966A1
公开(公告)日:2011-11-24
申请号:US12783200
申请日:2010-05-19
IPC分类号: H01L27/088 , H01L21/336
CPC分类号: H01L27/088 , H01L21/823418 , H01L21/823456 , H01L21/823493 , H01L29/4916 , H01L29/51 , H01L29/66545 , H01L29/66575 , H01L29/6659
摘要: The alignment mark and method for making the same are described. In one embodiment, a semiconductor structure includes a plurality of gate stacks formed on the semiconductor substrate and configured as an alignment mark; doped features formed in the semiconductor substrate and disposed on sides of each of the plurality of gate stacks; and channel regions underlying the plurality of gate stacks and free of channel dopant.
摘要翻译: 对准标记及其制作方法进行说明。 在一个实施例中,半导体结构包括形成在半导体衬底上并被配置为对准标记的多个栅叠层; 掺杂特征形成在所述半导体衬底中并且设置在所述多个栅极堆叠中的每一个的侧面上; 以及在多个栅极堆叠下面并且没有沟道掺杂剂的沟道区域。
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公开(公告)号:US08513821B2
公开(公告)日:2013-08-20
申请号:US12784581
申请日:2010-05-21
IPC分类号: H01L23/544 , H01L21/28
CPC分类号: H01L21/28 , G03F7/70633 , G03F7/70683 , H01L23/544 , H01L2223/54426 , H01L2223/54453 , H01L2924/0002 , H01L2924/00
摘要: A method and apparatus for alignment are disclosed. An exemplary apparatus includes a substrate having an alignment region; an alignment feature in the alignment region of the substrate; and a dummy feature disposed within the alignment feature. A dimension of the dummy feature is less than a resolution of an alignment mark detector.
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公开(公告)号:US20110285036A1
公开(公告)日:2011-11-24
申请号:US12784581
申请日:2010-05-21
IPC分类号: H01L23/544 , H01L21/28
CPC分类号: H01L21/28 , G03F7/70633 , G03F7/70683 , H01L23/544 , H01L2223/54426 , H01L2223/54453 , H01L2924/0002 , H01L2924/00
摘要: A method and apparatus for alignment are disclosed. An exemplary apparatus includes a substrate having an alignment region; an alignment feature in the alignment region of the substrate; and a dummy feature disposed within the alignment feature. A dimension of the dummy feature is less than a resolution of an alignment mark detector.
摘要翻译: 公开了一种用于对准的方法和装置。 示例性装置包括具有对准区域的基板; 在基板的对准区域中的对准特征; 以及设置在对准特征内的虚拟特征。 虚拟特征的尺寸小于对准标记检测器的分辨率。
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公开(公告)号:US08227150B2
公开(公告)日:2012-07-24
申请号:US12768405
申请日:2010-04-27
申请人: Shih-Ming Chang , Chung-Hsing Chang , Wen-Chuan Wang , Chi-Lun Lu , Sheng-Chi Chin , Chin-Hsiang Lin , Chun-Kuang Chen
发明人: Shih-Ming Chang , Chung-Hsing Chang , Wen-Chuan Wang , Chi-Lun Lu , Sheng-Chi Chin , Chin-Hsiang Lin , Chun-Kuang Chen
CPC分类号: G03F1/14 , G03F1/50 , G03F7/70283 , G03F7/70416 , G03H1/0005 , G03H1/0244 , G03H1/08 , G03H1/2205 , G03H2001/0094 , G03H2001/0833 , G03H2210/30 , G03H2224/04 , G03H2240/12 , G03H2240/13 , G03H2240/23 , G03H2270/52
摘要: A hologram reticle and method of patterning a target. A layout pattern for an image to be transferred to a target is converted into a holographic representation of the image. A hologram reticle is manufactured that includes the holographic representation. The hologram reticle is then used to pattern the target. Three-dimensional patterns may be formed in a photoresist layer of the target in a single patterning step. These three-dimensional patterns may be filled to form three-dimensional structures or else used in a multi-surface imaging composition. The holographic representation of the image may also be transferred to a top photoresist layer of a top surface imaging (TSI) semiconductor device, either directly or using the hologram reticle. The top photoresist layer may then be used to pattern an underlying photoresist layer with the image. The lower photoresist layer is used to pattern a material layer of the device.
摘要翻译: 全息图掩模版和图案化目标的方法。 要传输到目标的图像的布局图案被转换成图像的全息图。 制造包括全息图的全息标线。 然后使用全息图标线来对目标进行图案化。 可以在单个图案化步骤中在靶的光致抗蚀剂层中形成三维图案。 这些三维图案可以被填充以形成三维结构,或者用于多表面成像组合物中。 图像的全息图也可以直接地或使用全息图掩模图传递到顶表面成像(TSI)半导体器件的顶部光致抗蚀剂层。 然后可以使用顶部光致抗蚀剂层来用图像对下面的光致抗蚀剂层进行图案化。 下部光致抗蚀剂层用于对该器件的材料层进行图案化。
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8.
公开(公告)号:US20110193202A1
公开(公告)日:2011-08-11
申请号:US12701104
申请日:2010-02-05
申请人: Vincent Yu , Shih-Che Wang , Chun-Kuang Chen
发明人: Vincent Yu , Shih-Che Wang , Chun-Kuang Chen
摘要: Apparatus and methods are disclosed herein for fabricating semiconductor device features with a half-pitch node of 22 nm and beyond using single exposure and single etch (1P1E) photolithography techniques. The method includes exposing in a single exposure a photoresist layer to the exposure source through a photolithography mask where the photolithography mask has on it an island pattern of a material having high percentage transmission. The photoresist layer is developed using a negative tone developer to form a hole pattern in the photoresist layer. The 1P1E does not require the second photo exposure of the double patterning method. Furthermore, the method circumvents the island pattern collapsing issues and the need for strong illumination associated with exiting single 1P1E processes.
摘要翻译: 本文公开了用于制造半导体器件特征的装置和方法,其半节距节点为22nm,并且超过使用单次曝光和单蚀刻(1P1E)光刻技术。 该方法包括通过光刻掩膜将光致抗蚀剂层暴露于曝光源到曝光源,光刻掩模在其上具有透光率高的材料的岛状图案。 使用负色调显影剂显影光致抗蚀剂层以在光致抗蚀剂层中形成孔图案。 1P1E不需要双重图案化方法的第二次曝光。 此外,该方法避免了岛屿模式的崩溃问题以及与退出单个1P1E过程相关的强烈照明的需求。
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公开(公告)号:US20100297538A1
公开(公告)日:2010-11-25
申请号:US12768405
申请日:2010-04-27
申请人: Shih-Ming Chang , Chung-Hsing Chang , Wen-Chuan Wang , Chi-Lun Lu , Sheng-Chi Chin , Chin-Hsiang Lin , Chun-Kuang Chen
发明人: Shih-Ming Chang , Chung-Hsing Chang , Wen-Chuan Wang , Chi-Lun Lu , Sheng-Chi Chin , Chin-Hsiang Lin , Chun-Kuang Chen
CPC分类号: G03F1/14 , G03F1/50 , G03F7/70283 , G03F7/70416 , G03H1/0005 , G03H1/0244 , G03H1/08 , G03H1/2205 , G03H2001/0094 , G03H2001/0833 , G03H2210/30 , G03H2224/04 , G03H2240/12 , G03H2240/13 , G03H2240/23 , G03H2270/52
摘要: A hologram reticle and method of patterning a target. A layout pattern for an image to be transferred to a target is converted into a holographic representation of the image. A hologram reticle is manufactured that includes the holographic representation. The hologram reticle is then used to pattern the target. Three-dimensional patterns may be formed in a photoresist layer of the target in a single patterning step. These three-dimensional patterns may be filled to form three-dimensional structures or else used in a multi-surface imaging composition. The holographic representation of the image may also be transferred to a top photoresist layer of a top surface imaging (TSI) semiconductor device, either directly or using the hologram reticle. The top photoresist layer may then be used to pattern an underlying photoresist layer with the image. The lower photoresist layer is used to pattern a material layer of the device.
摘要翻译: 全息图掩模版和图案化目标的方法。 要传输到目标的图像的布局图案被转换成图像的全息图。 制造包括全息图的全息标线。 然后使用全息图标线来对目标进行图案化。 可以在单个图案化步骤中在靶的光致抗蚀剂层中形成三维图案。 这些三维图案可以被填充以形成三维结构,或者用于多表面成像组合物中。 图像的全息图也可以直接地或使用全息图掩模图传递到顶表面成像(TSI)半导体器件的顶部光致抗蚀剂层。 然后可以使用顶部光致抗蚀剂层来用图像对下面的光致抗蚀剂层进行图案化。 下部光致抗蚀剂层用于对该器件的材料层进行图案化。
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公开(公告)号:US07675604B2
公开(公告)日:2010-03-09
申请号:US11427434
申请日:2006-06-29
申请人: Li-Jui Chen , Tzung-Chi Fu , Ching-Yu Chang , Fu-Jye Liang , Lin-Hung Shiu , Chun-Kuang Chen , Tsai-Sheng Gau
发明人: Li-Jui Chen , Tzung-Chi Fu , Ching-Yu Chang , Fu-Jye Liang , Lin-Hung Shiu , Chun-Kuang Chen , Tsai-Sheng Gau
CPC分类号: G03F7/70341
摘要: A lithography apparatus includes an imaging lens module; a substrate table positioned underlying the imaging lens module and configured to hold a substrate; a fluid retaining module configured to hold a fluid in a space between the imaging lens module and a substrate on the substrate stage; and a heating element configured in the fluid retaining module and adjacent to the space. The heating element includes at least two of following: a sealant insoluble to the fluid for sealing the heating element in the fluid retaining module; a sealed opening configured in one of top portion and side portion of the fluid retaining module for sealing the heating element in the fluid retaining module; and/or a non-uniform temperature compensation device configured with the heating element.
摘要翻译: 光刻设备包括成像透镜模块; 位于所述成像透镜模块下方且被配置为保持基板的基板台; 流体保持模块,被配置为将流体保持在所述成像透镜模块和所述基板载台上的基板之间的空间中; 以及配置在所述流体保持模块中且与所述空间相邻的加热元件。 所述加热元件包括以下至少两个:对所述流体不溶的密封剂,用于密封所述流体保持模块中的所述加热元件; 密封开口,其构造在流体保持模块的顶部和侧部之一中,用于密封流体保持模块中的加热元件; 和/或配置有加热元件的不均匀的温度补偿装置。
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