公开(公告)号：US20060169976A1

公开(公告)日：2006-08-03

申请号：US11325546

申请日：2006-01-05

申请人： Mitsuhiro Kameda ,  Makoto Yokota

发明人： Mitsuhiro Kameda ,  Makoto Yokota

IPC分类号： H01L29/10

CPC分类号： H01L29/7813 ,  H01L23/36 ,  H01L23/49575 ,  H01L23/552 ,  H01L24/37 ,  H01L24/40 ,  H01L24/41 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L29/4175 ,  H01L29/7806 ,  H01L29/7835 ,  H01L2224/05554 ,  H01L2224/32245 ,  H01L2224/33181 ,  H01L2224/371 ,  H01L2224/37147 ,  H01L2224/37599 ,  H01L2224/40225 ,  H01L2224/45014 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/49171 ,  H01L2224/73221 ,  H01L2224/73265 ,  H01L2224/83205 ,  H01L2224/83801 ,  H01L2224/84205 ,  H01L2224/84801 ,  H01L2225/06562 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/12032 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207

摘要： A semiconductor device comprises: a first semiconductor chip having a first MIS transistor of a first conductivity type and a second semiconductor chip having a second MIS transistor of the first conductivity type. The first MIS transistor has a source electrode formed on a first face. The second MIS transistor has a drain electrode formed on a first face. The source electrode of the first semiconductor chip and the drain electrode of the second semiconductor chip are bonded opposite to each other.

摘要翻译： 半导体器件包括：具有第一导电类型的第一MIS晶体管的第一半导体芯片和具有第一导电类型的第二MIS晶体管的第二半导体芯片。 第一MIS晶体管具有形成在第一面上的源电极。 第二MIS晶体管具有形成在第一面上的漏电极。 第一半导体芯片的源电极和第二半导体芯片的漏电极彼此相对地接合。

公开(公告)号：US07042026B2

公开(公告)日：2006-05-09

申请号：US10933543

申请日：2004-09-03

申请人： Mitsuhiro Kameda

发明人： Mitsuhiro Kameda

IPC分类号： H01L29/74 ,  H01L31/111

CPC分类号： H02M3/158 ,  H01L29/42372 ,  H01L29/7802 ,  H02M3/00 ,  H02M2001/0009

摘要： A power switching device comprises a semiconductor substrate; a plurality of cells, each of which switches a current from a power supply to a load on the basis of a potential at a gate electrode, said cells being arranged on said semiconductor substrate to form a cell array; and a plurality of drivers connected to the gate electrode, said plurality of drivers being distributively arranged in said cell array or being distributively arranged peripheral said cell array.

摘要翻译： 电源开关器件包括半导体衬底; 多个单元，其中每个单元基于栅电极的电位将电流从电源切换到负载，所述单元布置在所述半导体衬底上以形成单元阵列; 以及连接到所述栅电极的多个驱动器，所述多个驱动器被分布地布置在所述单元阵列中或者被分布地布置在所述单元阵列周围。

公开(公告)号：US06809387B2

公开(公告)日：2004-10-26

申请号：US10410408

申请日：2003-04-10

申请人： Mitsuhiro Kameda

发明人： Mitsuhiro Kameda

IPC分类号： H01L2976

CPC分类号： H02M3/158 ,  H01L29/42372 ,  H01L29/7802 ,  H02M3/00 ,  H02M2001/0009

摘要： A power switching device comprises a semiconductor substrate; a plurality of cells, each of which switches a current from a power supply to a load on the basis of a potential at a gate electrode, said cells being arranged on said semiconductor substrate to form a cell array; and a plurality of drivers connected to the gate electrode, said plurality of drivers being distributively arranged in said cell array or being distributively arranged peripheral said cell array.

公开(公告)号：US20050023618A1

公开(公告)日：2005-02-03

申请号：US10933543

申请日：2004-09-03

申请人： Mitsuhiro Kameda

发明人： Mitsuhiro Kameda

IPC分类号： H02M3/155 ,  H01L29/423 ,  H01L29/78 ,  H02M3/00 ,  H02M3/158 ,  H02M3/335

CPC分类号： H02M3/158 ,  H01L29/42372 ,  H01L29/7802 ,  H02M3/00 ,  H02M2001/0009

摘要： A power switching device comprises a semiconductor substrate; a plurality of cells, each of which switches a current from a power supply to a load on the basis of a potential at a gate electrode, said cells being arranged on said semiconductor substrate to form a cell array; and a plurality of drivers connected to the gate electrode, said plurality of drivers being distributively arranged in said cell array or being distributively arranged peripheral said cell array.

摘要翻译： 电源开关器件包括半导体衬底; 多个单元，其中每个单元基于栅电极的电位将电流从电源切换到负载，所述单元布置在所述半导体衬底上以形成单元阵列; 以及连接到所述栅电极的多个驱动器，所述多个驱动器被分布地布置在所述单元阵列中或者被分布地布置在所述单元阵列周围。

公开(公告)号：US06867494B2

公开(公告)日：2005-03-15

申请号：US10438106

申请日：2003-05-15

申请人： Mitsuhiro Kameda ,  Koichi Sameshima

发明人： Mitsuhiro Kameda ,  Koichi Sameshima

IPC分类号： H01L25/18 ,  H01L21/60 ,  H01L23/52 ,  H01L25/04 ,  H01L25/16 ,  H01L29/417 ,  H01L29/78 ,  H01L23/34

CPC分类号： H01L29/7813 ,  H01L24/48 ,  H01L24/49 ,  H01L25/16 ,  H01L29/4175 ,  H01L29/41766 ,  H01L29/7806 ,  H01L29/7835 ,  H01L2223/6611 ,  H01L2224/05599 ,  H01L2224/48247 ,  H01L2224/4903 ,  H01L2224/49051 ,  H01L2224/49113 ,  H01L2224/49171 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/12032 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/30107 ,  Y10S257/901 ,  H01L2924/00 ,  H01L2224/45099

摘要： A semiconductor module includes a supporting substrate having a connecting section on a first major surface thereof. A first semiconductor chip includes a first MIS transistor a source of which is formed on the bottom thereof. A second semiconductor chip includes a second MIS transistor a drain of which is formed on the bottom thereof. The first and second semiconductor chips are on the supporting substrate such that the source of the first MIS transistor and the drain of the second MIS transistor are connected to the connecting section and connected each other through the connecting section. An IC chip is provided on the first major surface and connected to gates of the first and second MIS transistors. An insulative envelope covers the supporting substrate, first and second semiconductor chips and IC chip. Partly exposed connecting terminals are electrically connected to the connecting section and first and second semiconductor chips.

公开(公告)号：US06552390B2

公开(公告)日：2003-04-22

申请号：US10174999

申请日：2002-06-20

申请人： Mitsuhiro Kameda

发明人： Mitsuhiro Kameda

IPC分类号： H01L2976

CPC分类号： H01L29/7835 ,  H01L29/1045

摘要： A semiconductor device comprises a first conductivity type semiconductor substrate, a first conductivity type semiconductor layer formed on the substrate, a MISFET formed in a first area of the semiconductor layer, having a drain and source, and a gate electrode formed on a semiconductor layer between the drain and source through a gate insulator, an internal source electrode formed to contact the source and whose surface is covered with an insulating layer, a diode formed in a second area of the semiconductor layer, having a cathode and an anode provided on the cathode, an anode electrode which contacts the anode, a conductive portion piercing the semiconductor layer to electrically connect the internal source electrode and the cathode to the substrate, and a source/cathode electrode formed on the back plane of the substrate and commonly provided as a source electrode of the MISFET and a cathode electrode of the diode.

公开(公告)号：US07259459B2

公开(公告)日：2007-08-21

申请号：US10934451

申请日：2004-09-07

申请人： Mitsuhiro Kameda ,  Koichi Sameshima

发明人： Mitsuhiro Kameda ,  Koichi Sameshima

IPC分类号： H01L23/34

CPC分类号： H01L29/7813 ,  H01L24/48 ,  H01L24/49 ,  H01L25/16 ,  H01L29/4175 ,  H01L29/41766 ,  H01L29/7806 ,  H01L29/7835 ,  H01L2223/6611 ,  H01L2224/05599 ,  H01L2224/48247 ,  H01L2224/4903 ,  H01L2224/49051 ,  H01L2224/49113 ,  H01L2224/49171 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/12032 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/30107 ,  Y10S257/901 ,  H01L2924/00 ,  H01L2224/45099

摘要： A semiconductor module includes a supporting substrate having a connecting section on a first major surface thereof. A first semiconductor chip includes a first MIS transistor a source of which is formed on the bottom thereof. A second semiconductor chip includes a second MIS transistor a drain of which is formed on the bottom thereof. The first and second semiconductor chips are on the supporting substrate such that the source of the first MIS transistor and the drain of the second MIS transistor are connected to the connecting section and connected each other through the connecting section. An IC chip is provided on the first major surface and connected to gates of the first and second MIS transistors. An insulative envelope covers the supporting substrate, first and second semiconductor chips and IC chip. Partly exposed connecting terminals are electrically connected to the connecting section and first and second semiconductor chips.

摘要翻译： 半导体模块包括在其第一主表面上具有连接部分的支撑基板。 第一半导体芯片包括其底部形成有源极的第一MIS晶体管。 第二半导体芯片包括第二MIS晶体管，漏极形成在其底部。 第一和第二半导体芯片在支撑基板上，使得第一MIS晶体管的源极和第二MIS晶体管的漏极连接到连接部分并且通过连接部彼此连接。 IC芯片设置在第一主表面上并连接到第一和第二MIS晶体管的栅极。 绝缘外壳覆盖支撑基板，第一和第二半导体芯片和IC芯片。 部分露出的连接端子电连接到连接部分和第一和第二半导体芯片。

公开(公告)号：US20050029617A1

公开(公告)日：2005-02-10

申请号：US10934451

申请日：2004-09-07

申请人： Mitsuhiro Kameda ,  Koichi Sameshima

发明人： Mitsuhiro Kameda ,  Koichi Sameshima

IPC分类号： H01L25/18 ,  H01L21/60 ,  H01L23/52 ,  H01L25/04 ,  H01L25/16 ,  H01L29/417 ,  H01L29/78 ,  H01L29/40

CPC分类号： H01L29/7813 ,  H01L24/48 ,  H01L24/49 ,  H01L25/16 ,  H01L29/4175 ,  H01L29/41766 ,  H01L29/7806 ,  H01L29/7835 ,  H01L2223/6611 ,  H01L2224/05599 ,  H01L2224/48247 ,  H01L2224/4903 ,  H01L2224/49051 ,  H01L2224/49113 ,  H01L2224/49171 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/12032 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/30107 ,  Y10S257/901 ,  H01L2924/00 ,  H01L2224/45099

摘要： A semiconductor module includes a supporting substrate having a connecting section on a first major surface thereof. A first semiconductor chip includes a first MIS transistor a source of which is formed on the bottom thereof. A second semiconductor chip includes a second MIS transistor a drain of which is formed on the bottom thereof. The first and second semiconductor chips are on the supporting substrate such that the source of the first MIS transistor and the drain of the second MIS transistor are connected to the connecting section and connected each other through the connecting section. An IC chip is provided on the first major surface and connected to gates of the first and second MIS transistors. An insulative envelope covers the supporting substrate, first and second semiconductor chips and IC chip. Partly exposed connecting terminals are electrically connected to the connecting section and first and second semiconductor chips.

摘要翻译： 半导体模块包括在其第一主表面上具有连接部分的支撑基板。 第一半导体芯片包括其底部形成有源极的第一MIS晶体管。 第二半导体芯片包括第二MIS晶体管，其漏极形成在其底部。 第一和第二半导体芯片在支撑基板上，使得第一MIS晶体管的源极和第二MIS晶体管的漏极连接到连接部分并且通过连接部彼此连接。 IC芯片设置在第一主表面上并连接到第一和第二MIS晶体管的栅极。 绝缘外壳覆盖支撑基板，第一和第二半导体芯片和IC芯片。 部分露出的连接端子电连接到连接部分和第一和第二半导体芯片。