公开(公告)号：US6040001A

公开(公告)日：2000-03-21

申请号：US136614

申请日：1998-08-20

申请人： Mun Cheol Paek ,  Sung Woo Choi ,  Kee Soo Nam

发明人： Mun Cheol Paek ,  Sung Woo Choi ,  Kee Soo Nam

IPC分类号： H01L29/68 ,  H01J9/02 ,  H01J21/10 ,  B05D5/12 ,  C23C16/00

CPC分类号： H01J21/105 ,  H01J9/025 ,  H01J2201/30457

摘要： This invention discloses a method of manufacturing a diamond vacuum device, and more particularly a method of manufacturing a diamond vacuum device which uses a diamond thin film as an electron emitter by electric field. The present invention presents a method of manufacturing a vacuum device for use in high speed, high voltage, using diamond having a negative electron affinity, which can emit electrons even at a low voltage and is also resistant to chemical variations.

摘要翻译： 本发明公开了一种制造金刚石真空装置的方法，特别是一种制造金刚石真空装置的方法，金刚石真空装置通过电场使用金刚石薄膜作为电子发射体。 本发明提供了一种使用具有负电子亲和力的金刚石制造用于高速，高电压的真空装置的方法，其即使在低电压下也可以发射电子，并且也耐化学变化。

公开(公告)号：US6063201A

公开(公告)日：2000-05-16

申请号：US141557

申请日：1998-08-28

申请人： Hae Gwon Lee ,  Gyu Hwan Sim ,  Sung Woo Choi ,  Mun Cheol Baek ,  Kee Soo Nam

发明人： Hae Gwon Lee ,  Gyu Hwan Sim ,  Sung Woo Choi ,  Mun Cheol Baek ,  Kee Soo Nam

IPC分类号： H01L21/20 ,  C30B23/06 ,  C23C16/00

CPC分类号： C30B23/066

摘要： An effusion cell assembly for epitaxial apparatus is disclosed. The assembly includes an effusion cell incluing a growing material, a heater for supplying heats with the effusion cell to effuse the growing material, a supporting plate for supporting the heater, a bolt having one end connected to the supporting plate, a cell flange coupled to a lower flange of an adaptor for supporting the cell assembly, bellows fixed between the supporting plate and the cell flange including the bolt, and a control nut for expanding and contracting the bellows so as to separate only the cell assembly from a vacuum chamber with entire vacuum maintained in the vacuum chamber and local vacuum released in the cell assembly. The epitaxial apparatus further includes a control valve located between an entrance flange of the vacuum chamber and an upper adaptor flange of the adaptor for introducing and maintaining vacuum in the vacuum chamber.

摘要翻译： 公开了一种用于外延设备的渗流池组件。 组件包括包含生长材料的积液池，用于向渗出池供应热量以加热生长材料的加热器，用于支撑加热器的支撑板，具有连接到支撑板的一端的螺栓，耦合到 用于支撑电池组件的适配器的下凸缘，固定在支撑板和包括螺栓的电池凸缘之间的波纹管，以及用于膨胀和收缩波纹管的控制螺母，以便仅将电池组件与真空室整体分离 在真空室中保持真空并在电池组件中释放局部真空。 外延装置还包括位于真空室的入口凸缘和适配器的上适配器凸缘之间的控制阀，用于在真空室中引入和保持真空。

公开(公告)号：US6087232A

公开(公告)日：2000-07-11

申请号：US135645

申请日：1998-08-18

申请人： Jong Dae Kim ,  Sang Ki Kim ,  Jin Gun Koo ,  Kee Soo Nam

发明人： Jong Dae Kim ,  Sang Ki Kim ,  Jin Gun Koo ,  Kee Soo Nam

IPC分类号： H01L21/02 ,  H01L21/336 ,  H01L29/78

CPC分类号： H01L29/66659 ,  H01L29/7835

摘要： According to a method for manufacturing double RESURF (reduced SURface Field) LDMOS (Lateral Diffused Metal Oxide Semiconductor) transistors, on-resistance of double RESURF LDMOS transistors has been improved by using a new tapered p top layer on the surface of the drift region of the transistor, thereby decreasing the length of the drift region. Another advantage of the current invention is that the breakdown voltage similar with the on-resistance can be improved by using a reproducible tapered TEOS oxide by use of a multi-layer structure and low temperature annealing process. This is due to the reducing of the current path and impurity segregation in the drift region by using the tapered TEOS oxide instead of LOCOS filed oxide.

摘要翻译： 根据制造双RESURF（减少的SURface Field）LDMOS（侧向扩散金属氧化物半导体）晶体管的方法，通过在漂移区的表面上使用新的锥形p顶层，改善了双RESURF LDMOS晶体管的导通电阻 晶体管，从而减小漂移区的长度。 本发明的另一个优点是可以通过使用多层结构和低温退火工艺使用可再现的锥形TEOS氧化物来改善与导通电阻相似的击穿电压。 这是由于通过使用锥形TEOS氧化物而不是LOCOS氧化物来减少漂移区中的电流路径和杂质偏析。

公开(公告)号：US6093599A

公开(公告)日：2000-07-25

申请号：US232691

申请日：1999-01-19

申请人： Jin Hyo Lee ,  Heung Soo Rhee ,  Hyun Kyu Yu ,  Bo Woo Kim ,  Kee Soo Nam

发明人： Jin Hyo Lee ,  Heung Soo Rhee ,  Hyun Kyu Yu ,  Bo Woo Kim ,  Kee Soo Nam

IPC分类号： H01L21/76 ,  H01L21/763 ,  H01L21/822 ,  H01L27/04 ,  H01L27/08 ,  H01L21/8234

CPC分类号： H01L21/763 ,  H01L27/08

摘要： The present invention relates to a on silicon substrate, specifically to an inductor device and manufacturing method thereof for enhancing the quality factor of the inductor by disposing trenches on a silicon substratre, and by filling the inside of the trenches with polycrystalline polysilicon not doped with impurities. The present invention provides an inductor device and a manufacturing method thereof which can improve the quality factor by increasing resistance of the substrate by forming deep trenches disposed in specific patterns on a low-resistance silicon substrate and filling polycrystalline silicon not doped with impurities, and by reducing parasitic capacitance between the inductor and the silicon substrate.

摘要翻译： 本发明涉及一种硅衬底，具体涉及一种电感器件及其制造方法，用于通过在硅衬底上设置沟槽来提高电感器的品质因数，并且通过用不掺杂杂质的多晶多晶硅填充沟槽内部 。 本发明提供一种电感器件及其制造方法，其可以通过在低电阻硅衬底上形成以特定图案设置的深沟槽并填充未掺杂杂质的多晶硅，并且通过 降低电感器和硅衬底之间的寄生电容。

公开(公告)号：US06534365B2

公开(公告)日：2003-03-18

申请号：US09726910

申请日：2000-11-29

申请人： Jong Dae Kim ,  Sang Gi Kim ,  Jin Gun Koo ,  Kee Soo Nam ,  Dae Woo Lee ,  Tae Moon Roh

发明人： Jong Dae Kim ,  Sang Gi Kim ,  Jin Gun Koo ,  Kee Soo Nam ,  Dae Woo Lee ,  Tae Moon Roh

IPC分类号： H01L21336

CPC分类号： H01L29/7813 ,  H01L29/0847 ,  H01L29/42368

摘要： A method of fabricating a vertical TDMOS power device using sidewall spacers and a self-align technique and a TDMOS power device of the same. The TDMOS is fabricated using only 3 masks and a source is formed using the self-align technique to embody a highly integrated trench formation. During the process, ion implantation of high concentration into the bottom of the trench makes a thick oxide film grow on the bottom and the corner of the gate, so that electrical characteristic, specifically leakage current and breakdown voltage of the device can be improved. Also, process steps can be much decreased to lower process cost, high integration is possible, and reliability of the device can be improved.

摘要翻译： 使用侧壁间隔物和自对准技术制造垂直TDMOS功率器件的方法以及使用其的TDMOS功率器件。 TDMOS仅使用3个掩模制造，并且使用自对准技术形成源以体现高度集成的沟槽形成。 在此过程中，高浓度离子注入沟槽的底部使得厚的氧化膜在栅极的底部和拐角处生长，从而可以提高器件的电气特性，特别是漏电流和击穿电压。 此外，可以大大降低工艺步骤以降低工艺成本，可以实现高集成度，并且可以提高器件的可靠性。

公开(公告)号：US06211018B1

公开(公告)日：2001-04-03

申请号：US09475281

申请日：1999-12-30

申请人： Kee Soo Nam ,  Sang Gi Kim ,  Tae Moon Roh ,  Jin Gun Koo

发明人： Kee Soo Nam ,  Sang Gi Kim ,  Tae Moon Roh ,  Jin Gun Koo

IPC分类号： H01L21336

CPC分类号： H01L29/66727 ,  H01L29/66348

摘要： A semiconductor technique is disclosed. Particularly a low voltage high current power device for use in a lithium ion secondary battery protecting circuit, a DC-DC converter and a motor is disclosed. Further, a method for fabricating a high density trench gate type power device is disclosed. That is, in the present invention, a trench gate mask is used for forming the well and/or source, and for this purpose, a side wall spacer is introduced. In this manner, the well and/or source is defined by using the trench gate mask, and therefore, 1 or 2 masking processes are skipped unlike the conventional process in which the well mask and the source mask are separately used. The decrease in the use of the masking process decreases the mask align errors, and therefore, the realization of a high density is rendered possible. Consequently, the on-resistance which is an important factor for the power device can be lowered.

摘要翻译： 公开了半导体技术。 特别地，公开了一种用于锂离子二次电池保护电路，DC-DC转换器和电动机的低压大电流功率器件。 此外，公开了一种制造高密度沟槽栅型功率器件的方法。 也就是说，在本发明中，沟槽栅极掩模用于形成阱和/或源，为此，引入了侧壁间隔物。 以这种方式，通过使用沟槽栅极掩模来定义阱和/或源，因此与分开使用阱掩模和源掩模的常规工艺不同，跳过1或2个屏蔽处理。 掩蔽过程的使用减少会降低掩模对准误差，因此可以实现高密度。 因此，作为功率器件的重要因素的导通电阻可以降低。

公开(公告)号：US6008097A

公开(公告)日：1999-12-28

申请号：US989033

申请日：1997-12-11

申请人： Yong Sun Yoon ,  Kyu Ha Baek ,  Kee Soo Nam

发明人： Yong Sun Yoon ,  Kyu Ha Baek ,  Kee Soo Nam

IPC分类号： H01L29/786 ,  H01L21/225 ,  H01L21/28 ,  H01L21/336 ,  H01L21/768 ,  H01L29/423

CPC分类号： H01L29/66606 ,  H01L21/28114 ,  H01L21/76895 ,  H01L21/2257 ,  H01L29/42376

摘要： The present invention relates to a MOS transistor of semiconductor device and method of manufacturing the same and, in particular, to MOS a transistor of semiconductor device and method of manufacturing the same which can reduce asymmetry of drain current due to bias of drain current, facilitate shallow junction and reduce the area to a minimum by forming a source/drain.

摘要翻译： 本发明涉及一种半导体器件的MOS晶体管及其制造方法，特别是涉及MOS半导体器件的晶体管及其制造方法，其可以减少由于漏极电流的偏置导致的漏极电流的不对称性 浅结，并通过形成源极/漏极将面积减小到最小。