公开(公告)号：US20160133732A1

公开(公告)日：2016-05-12

申请号：US14988016

申请日：2016-01-05

Applicant: MURATA MANUFACTURING CO., LTD.

Inventor： Yasunari UMEMOTO ,  Atsushi KUROKAWA ,  Tsunekazu SAIMEI

IPC: H01L29/737 ,  H01L29/10 ,  H01L29/205 ,  H01L29/08

CPC classification number: H01L29/7371 ,  H01L29/0817 ,  H01L29/0821 ,  H01L29/1004 ,  H01L29/122 ,  H01L29/205 ,  H01L29/36 ,  H01L29/66242 ,  H01L29/6631

Abstract: In a bipolar transistor, a collector layer includes three semiconductor layers: an n-type GaAs layer (Si concentration: about 5×1015 cm−3, thickness: about 350 nm), a p-type GaAs layer (C concentration: about 4.5×1015 cm−3, thickness: about 100 nm, sheet concentration: 4.5×1010 cm−2), and an n-type GaAs layer Si concentration: about 5×1015 cm−3, thickness: about 500 nm. The sheet concentration of the p-type GaAs layer is set to less than 1×1011 cm−2.

Abstract translation: 在双极晶体管中，集电极层包括三个半导体层：n型GaAs层（Si浓度：约5×10 15 cm -3，厚度：约350nm），p型GaAs层（C浓度：约4.5 ×1015cm-3，厚度：约100nm，片材浓度：4.5×10 10 cm -2），n型GaAs层Si浓度约5×10 15 cm -3，厚度约500nm。 p型GaAs层的片材浓度设定为小于1×1011cm-2。

公开(公告)号：US20190067460A1

公开(公告)日：2019-02-28

申请号：US16171088

申请日：2018-10-25

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Yasunari UMEMOTO ,  Atsushi KUROKAWA ,  Tsunekazu SAIMEI

IPC: H01L29/737 ,  H01L29/12 ,  H01L29/66 ,  H01L29/36 ,  H01L29/08 ,  H01L29/205 ,  H01L29/10

Abstract: In a bipolar transistor, a collector layer includes three semiconductor layers: an n-type GaAs layer (Si concentration: about 5×1015 cm−3, thickness: about 350 nm), a p-type GaAs layer (C concentration: about 4.5×1015 cm−3, thickness: about 100 nm, sheet concentration: 4.5×1010 cm−2), and an n-type GaAs layer Si concentration: about 5×1015 cm−3, thickness: about 500 nm. The sheet concentration of the p-type GaAs layer is set to less than 1×1011 cm−2.

公开(公告)号：US20210184022A1

公开(公告)日：2021-06-17

申请号：US17189043

申请日：2021-03-01

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Yasunari UMEMOTO ,  Daisuke TOKUDA ,  Tsunekazu SAIMEI ,  Hiroaki TOKUYA

IPC: H01L29/737 ,  H01L29/417 ,  H01L29/732 ,  H01L23/00 ,  H01L29/06 ,  H01L29/08 ,  H01L29/66 ,  H01L29/20 ,  H01L29/205

Abstract: A semiconductor device that includes a bipolar transistor, wherein a third opening, through which a pillar bump and a second wiring line, which is electrically connected to an emitter layer, contact each other, is shifted in a longitudinal direction of the emitter layer away from a position at which the third opening would be directly above the emitter layer. The third opening is arranged, with respect to the emitter layer, such that an end portion of the emitter layer in the longitudinal direction of the emitter layer and the edge of the opening of the third opening are substantially aligned with each other.

公开(公告)号：US20190333887A1

公开(公告)日：2019-10-31

申请号：US16505390

申请日：2019-07-08

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Yasunari UMEMOTO ,  Daisuke TOKUDA ,  Tsunekazu SAIMEI ,  Hiroaki TOKUYA

IPC: H01L23/00 ,  H01L29/205 ,  H01L29/732 ,  H01L29/737 ,  H01L29/66 ,  H01L29/20 ,  H01L29/08 ,  H01L29/06 ,  H01L29/417

Abstract: A semiconductor device that includes a bipolar transistor, wherein a third opening, through which a pillar bump and a second wiring line, which is electrically connected to an emitter layer, contact each other, is shifted in a longitudinal direction of the emitter layer away from a position at which the third opening would be directly above the emitter layer. The third opening is arranged, with respect to the emitter layer, such that an end portion of the emitter layer in the longitudinal direction of the emitter layer and the edge of the opening of the third opening are substantially aligned with each other.

公开(公告)号：US20180233475A1

公开(公告)日：2018-08-16

申请号：US15954420

申请日：2018-04-16

Applicant: MURATA MANUFACTURING CO., LTD.

Inventor： Yasunari UMEMOTO ,  Daisuke TOKUDA ,  Tsunekazu SAIMEI ,  Hiroaki TOKUYA

IPC: H01L23/00 ,  H01L29/08 ,  H01L29/737 ,  H01L29/66 ,  H01L29/20 ,  H01L29/732 ,  H01L29/205 ,  H01L29/417

CPC classification number: H01L24/13 ,  H01L24/02 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/16 ,  H01L29/0692 ,  H01L29/0817 ,  H01L29/20 ,  H01L29/205 ,  H01L29/41708 ,  H01L29/66234 ,  H01L29/66242 ,  H01L29/66272 ,  H01L29/6631 ,  H01L29/66318 ,  H01L29/732 ,  H01L29/737 ,  H01L29/7371 ,  H01L29/7375 ,  H01L29/7378 ,  H01L2224/02331 ,  H01L2224/0235 ,  H01L2224/02372 ,  H01L2224/02373 ,  H01L2224/0239 ,  H01L2224/024 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05022 ,  H01L2224/05024 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05558 ,  H01L2224/05559 ,  H01L2224/05569 ,  H01L2224/05572 ,  H01L2224/05666 ,  H01L2224/1134 ,  H01L2224/13013 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/13026 ,  H01L2224/13083 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13563 ,  H01L2224/13611 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2924/00012 ,  H01L2924/01029 ,  H01L2924/07025 ,  H01L2924/10329 ,  H01L2924/10337 ,  H01L2924/10338 ,  H01L2924/13051 ,  H01L2924/13055 ,  H01L2924/1423 ,  H01L2924/351 ,  H01L2924/01079 ,  H01L2924/00014 ,  H01L2924/014

Abstract: A semiconductor device that includes a bipolar transistor, wherein a third opening, through which a pillar bump and a second wiring line, which is electrically connected to an emitter layer, contact each other, is shifted in a longitudinal direction of the emitter layer away from a position at which the third opening would be directly above the emitter layer. The third opening is arranged, with respect to the emitter layer, such that an end portion of the emitter layer in the longitudinal direction of the emitter layer and the edge of the opening of the third opening are substantially aligned with each other.

公开(公告)号：US20170077054A1

公开(公告)日：2017-03-16

申请号：US15361336

申请日：2016-11-25

Applicant: MURATA MANUFACTURING CO., LTD.

Inventor： Yasunari UMEMOTO ,  Daisuke TOKUDA ,  Tsunekazu SAIMEI ,  Hiroaki TOKUYA

IPC: H01L23/00 ,  H01L29/20 ,  H01L29/205 ,  H01L29/737

CPC classification number: H01L24/13 ,  H01L24/02 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/16 ,  H01L29/0692 ,  H01L29/0817 ,  H01L29/20 ,  H01L29/205 ,  H01L29/41708 ,  H01L29/66234 ,  H01L29/66242 ,  H01L29/66272 ,  H01L29/6631 ,  H01L29/66318 ,  H01L29/732 ,  H01L29/737 ,  H01L29/7371 ,  H01L29/7375 ,  H01L29/7378 ,  H01L2224/02331 ,  H01L2224/0235 ,  H01L2224/02372 ,  H01L2224/02373 ,  H01L2224/0239 ,  H01L2224/024 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05022 ,  H01L2224/05024 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05558 ,  H01L2224/05559 ,  H01L2224/05569 ,  H01L2224/05572 ,  H01L2224/05666 ,  H01L2224/1134 ,  H01L2224/13013 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/13026 ,  H01L2224/13083 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13563 ,  H01L2224/13611 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2924/00012 ,  H01L2924/01029 ,  H01L2924/07025 ,  H01L2924/10329 ,  H01L2924/10337 ,  H01L2924/10338 ,  H01L2924/13051 ,  H01L2924/13055 ,  H01L2924/1423 ,  H01L2924/351 ,  H01L2924/01079 ,  H01L2924/00014 ,  H01L2924/014

Abstract: A semiconductor device that includes a bipolar transistor, wherein a third opening, through which a pillar bump and a second wiring line, which is electrically connected to an emitter layer, contact each other, is shifted in a longitudinal direction of the emitter layer away from a position at which the third opening would be directly above the emitter layer. The third opening is arranged, with respect to the emitter layer, such that an end portion of the emitter layer in the longitudinal direction of the emitter layer and the edge of the opening of the third opening are substantially aligned with each other.

Abstract translation: 一种包括双极晶体管的半导体器件，其中与发射极层电连接的柱凸起和第二布线彼此接触的第三开口在发射极层的纵向方向上偏离 第三开口直接位于发射极层上方的位置。 第三开口相对于发射极层布置成使得发射极层的纵向方向上的发射极层的端部和第三开口的开口的边缘基本上彼此对准。

公开(公告)号：US20160315060A1

公开(公告)日：2016-10-27

申请号：US15202749

申请日：2016-07-06

Applicant: MURATA MANUFACTURING CO., LTD.

Inventor： Yasunari UMEMOTO ,  Daisuke TOKUDA ,  Tsunekazu SAIMEI ,  Hiroaki TOKUYA

IPC: H01L23/00 ,  H01L29/737

CPC classification number: H01L24/13 ,  H01L24/02 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/16 ,  H01L29/0692 ,  H01L29/0817 ,  H01L29/20 ,  H01L29/205 ,  H01L29/41708 ,  H01L29/66234 ,  H01L29/66242 ,  H01L29/66272 ,  H01L29/6631 ,  H01L29/66318 ,  H01L29/732 ,  H01L29/737 ,  H01L29/7371 ,  H01L29/7375 ,  H01L29/7378 ,  H01L2224/02331 ,  H01L2224/0235 ,  H01L2224/02372 ,  H01L2224/02373 ,  H01L2224/0239 ,  H01L2224/024 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05022 ,  H01L2224/05024 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05558 ,  H01L2224/05559 ,  H01L2224/05569 ,  H01L2224/05572 ,  H01L2224/05666 ,  H01L2224/1134 ,  H01L2224/13013 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/13026 ,  H01L2224/13083 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13563 ,  H01L2224/13611 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2924/00012 ,  H01L2924/01029 ,  H01L2924/07025 ,  H01L2924/10329 ,  H01L2924/10337 ,  H01L2924/10338 ,  H01L2924/13051 ,  H01L2924/13055 ,  H01L2924/1423 ,  H01L2924/351 ,  H01L2924/01079 ,  H01L2924/00014 ,  H01L2924/014

Abstract: A semiconductor device that includes a bipolar transistor, wherein a third opening, through which a pillar bump and a second wiring line, which is electrically connected to an emitter layer, contact each other, is shifted in a longitudinal direction of the emitter layer away from a position at which the third opening would be directly above the emitter layer. The third opening is arranged, with respect to the emitter layer, such that an end portion of the emitter layer in the longitudinal direction of the emitter layer and the edge of the opening of the third opening are substantially aligned with each other.

Abstract translation: 一种包括双极晶体管的半导体器件，其中与发射极层电连接的柱凸起和第二布线彼此接触的第三开口在发射极层的纵向方向上偏离 第三开口直接位于发射极层上方的位置。 第三开口相对于发射极层布置成使得发射极层的纵向方向上的发射极层的端部和第三开口的开口的边缘基本上彼此对准。

公开(公告)号：US20150349100A1

公开(公告)日：2015-12-03

申请号：US14821214

申请日：2015-08-07

Applicant: MURATA MANUFACTURING CO., LTD.

Inventor： Yasunari UMEMOTO ,  Atsushi KUROKAWA ,  Tsunekazu SAIMEI

IPC: H01L29/732

CPC classification number: H01L29/7325 ,  H01L29/0821 ,  H01L29/152 ,  H01L29/20 ,  H01L29/7371

Abstract: P-type second semiconductor layers each interposed between a corresponding pair of n-type first semiconductor layers reduce the apparent doping concentration in the entire collector layer without reducing the doping concentrations in the first semiconductor layers. This improves the linearity of capacitance characteristics and enables sufficient mass productivity to be achieved. Interposing each of the second semiconductor layers between the corresponding pair of the first semiconductor layers reduce the average carrier concentration over the entire collector layer, which allows a wide depletion layer to be formed inside the collector layer and, as a result, reduces base-collector capacitance.

Abstract translation: 各自插入相应的一对n型第一半导体层之间的P型第二半导体层降低了整个集电极层中的表观掺杂浓度，而不降低第一半导体层中的掺杂浓度。 这提高了电容特性的线性，并且能够实现足够的批量生产率。 将相应的第一半导体层之间的每一个第二半导体层插入整个集电极层上的平均载流子浓度，这允许在集电极层内形成宽的耗尽层，结果减少了基极集电极 电容。