公开(公告)号：US20210259105A1

公开(公告)日：2021-08-19

申请号：US17307300

申请日：2021-05-04

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Ryota ASAI ,  Yosuke MATSUSHITA

IPC: H05K1/11 ,  H01L25/00 ,  H05K1/03 ,  H05K3/38 ,  H01L21/56 ,  H05K3/46 ,  H01L21/48 ,  H01L23/31 ,  H01L23/498 ,  H05K1/18 ,  H05K3/00 ,  H05K3/40 ,  H05K5/06

Abstract: A ceramic substrate of the present disclosure is a ceramic substrate including a ceramic body having a ceramic layer on a surface thereof and a surface electrode placed on a primary face of the ceramic body. Between the surface electrode and the ceramic layer is an oxide layer made of an insulating oxide having a melting point higher than the firing temperature for the ceramic layer. The oxide layer also extends on the ceramic layer not occupied by the surface electrode. The oxide layer on the ceramic layer not occupied by the surface electrode has a rough surface.

公开(公告)号：US20190191562A1

公开(公告)日：2019-06-20

申请号：US16281269

申请日：2019-02-21

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Ryota ASAI ,  Yosuke MATSUSHITA

IPC: H05K1/11 ,  H05K1/03 ,  H01L23/498 ,  H05K5/06 ,  H05K1/18 ,  H01L23/31 ,  H01L23/15 ,  H05K3/40 ,  H05K3/38 ,  H05K3/00 ,  H01L21/48

CPC classification number: H05K1/111 ,  C04B41/90 ,  H01L21/4853 ,  H01L23/13 ,  H01L23/15 ,  H01L23/3121 ,  H01L23/49811 ,  H01L23/49894 ,  H01L25/00 ,  H05K1/03 ,  H05K1/0306 ,  H05K1/181 ,  H05K3/0044 ,  H05K3/38 ,  H05K3/381 ,  H05K3/4007 ,  H05K3/46 ,  H05K5/065

Abstract: A ceramic substrate of the present disclosure is a ceramic substrate including a ceramic body having a ceramic layer on a surface thereof and a surface electrode placed on a primary face of the ceramic body. Between the surface electrode and the ceramic layer is an oxide layer made of an insulating oxide having a melting point higher than the firing temperature for the ceramic layer. The oxide layer also extends on the ceramic layer not occupied by the surface electrode. The oxide layer on the ceramic layer not occupied by the surface electrode has a rough surface.

公开(公告)号：US20220117084A1

公开(公告)日：2022-04-14

申请号：US17645323

申请日：2021-12-21

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Ryota ASAI ,  Yosuke MATSUSHITA

IPC: H05K1/11 ,  H01L25/00 ,  H05K1/03 ,  H05K3/38 ,  H01L21/56 ,  H05K3/46 ,  H01L21/48 ,  H01L23/31 ,  H01L23/498 ,  H05K1/18 ,  H05K3/00 ,  H05K3/40 ,  H05K5/06

Abstract: A ceramic substrate of the present disclosure is a ceramic substrate including a ceramic body having a ceramic layer on a surface thereof and a surface electrode placed on a primary face of the ceramic body. Between the surface electrode and the ceramic layer is an oxide layer made of an insulating oxide having a melting point higher than the firing temperature for the ceramic layer. The oxide layer also extends on the ceramic layer not occupied by the surface electrode. The oxide layer on the ceramic layer not occupied by the surface electrode has a rough surface.

公开(公告)号：US20200027825A1

公开(公告)日：2020-01-23

申请号：US16585180

申请日：2019-09-27

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Ryota ASAI ,  Issei YAMAMOTO

IPC: H01L23/498 ,  H01L25/16 ,  H01L21/48

Abstract: A wiring substrate that is provided enables stray capacitance between a first electrode and a second electrode to be prevented from varying when an undulation occurs in the wiring substrate. Insulating layers are stacked. A first electrode and a second electrode are formed between the same layers at an interval. The thickness of the first electrode is more than the thickness of the second electrode. The lower main surface of the first electrode is located at a position lower than the lower main surface of the second electrode, and the upper main surface of the first electrode is located at a position higher than the upper main surface of the second electrode when seen through in a direction perpendicular to a stacking direction of the insulating layers.

公开(公告)号：US20200083587A1

公开(公告)日：2020-03-12

申请号：US16682510

申请日：2019-11-13

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Yosuke MATSUSHITA ,  Ryota ASAI

IPC: H01P5/18 ,  H01F27/28 ,  H01F27/29 ,  H01F41/04 ,  H01P11/00

Abstract: A multilayer electronic component includes an element body including a plurality of base layers stacked in a first direction, an inner conductor disposed in the element body, and a mounting terminal connected to the inner conductor. The multilayer electronic component has a mount surface positioned on a mounted side when the multilayer electronic component is mounted. The mount surface is disposed so as not to intersect an axis along the first direction. The mounting terminal is disposed on the mount surface and embedded from the mount surface into the element body.

公开(公告)号：US20160242286A1

公开(公告)日：2016-08-18

申请号：US15135638

申请日：2016-04-22

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Ryota ASAI

IPC: H05K1/11 ,  H05K3/10 ,  H05K1/09 ,  H05K1/02 ,  H05K1/03

CPC classification number: H05K1/115 ,  H05K1/0298 ,  H05K1/0306 ,  H05K1/038 ,  H05K1/09 ,  H05K3/108 ,  H05K3/244 ,  H05K3/28 ,  H05K2201/0145 ,  H05K2201/0195 ,  H05K2201/0338 ,  H05K2201/0391 ,  H05K2201/099 ,  H05K2201/09909

Abstract: A wiring board is provided with: an insulating layer; a base electrode layer layered on one primary surface of the insulating layer in predetermined regions; an insulating covering layer layered on one primary surface of the insulating layer in a state covering parts of edges of the base electrode layer; and a surface electrode layer plated on exposed portions of the base electrode layer not covered by the insulating covering layer, the thickness of covered portions of the base electrode layer covered by the insulating covering layer being less than the thickness of the exposed portions. The surface electrode layer is formed only on the exposed portions of the base electrode layer.

Abstract translation: 布线板设有：绝缘层; 在预定区域中在绝缘层的一个主表面上层叠的基极层; 在覆盖所述基极电极层的边缘部分的状态下层叠在所述绝缘层的一个主面上的绝缘被覆层; 以及电镀在未被绝缘覆盖层覆盖的基极电极层的露出部分上的表面电极层，由绝缘覆盖层覆盖的基极层的被覆部分的厚度小于露出部分的厚度。 表面电极层仅形成在基极层的露出部分上。