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公开(公告)号:US20190280181A1
公开(公告)日:2019-09-12
申请号:US16419219
申请日:2019-05-22
Applicant: Murata Manufacturing Co., Ltd.
Inventor: Yasuhiro Aida , Daiki Murauchi
IPC: H01L41/047 , H01L41/08 , H01L41/083
Abstract: A piezoelectric element that includes a substrate, a lower electrode layer on the substrate, an intermediate layer on the lower electrode layer, and an upper electrode layer on the intermediate layer. The intermediate layer includes a first piezoelectric layer including an aluminum nitride as a main component thereof and located between the lower electrode layer and the upper electrode layer, a first buffer layer including an aluminum nitride as a main component and located between the first piezoelectric layer and the upper electrode layer, a first intermediate electrode layer located between the first buffer layer and the upper electrode layer, and a second piezoelectric layer located between the first intermediate electrode layer and the upper electrode layer.
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公开(公告)号:US12138658B2
公开(公告)日:2024-11-12
申请号:US17894217
申请日:2022-08-24
Applicant: Murata Manufacturing Co., Ltd.
Inventor: Fumiya Kurokawa , Yasuhiro Aida , Shinsuke Ikeuchi , Seiji Umezawa , Masayuki Suzuki
Abstract: An ultrasonic transducer includes first and second acoustic transducers and a housing with a bottomed tubular shape. The second acoustic transducer includes an annular section supporting a second membrane section and contacting an entire periphery of the second membrane section, and an acoustic matching plate facing the second membrane section and spaced apart from the second membrane section. The acoustic matching plate is connected to a surrounding wall portion defining a sealed space with the housing. An ultrasonic transmission path sandwiched between the first membrane section and the second membrane section is provided in the sealed space. A maximum inner width of the ultrasonic transmission path is smaller than a maximum inner width of the surrounding wall portion.
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公开(公告)号:US20190007026A1
公开(公告)日:2019-01-03
申请号:US16126248
申请日:2018-09-10
Applicant: Murata Manufacturing Co., Ltd. , National Institute of Advanced Industrial Science and Technology
Inventor: Keiichi Umeda , Takaaki Mizuno , Yasuhiro Aida , Masato Uehara , Toshimi Nagase , Morito Akiyama
IPC: H03H9/17 , H03H3/02 , H03H9/05 , H03H9/13 , H01L41/047 , H01L41/187 , H01L41/29 , H01L41/316
Abstract: A gallium nitride structure that includes: a substrate; a gallium nitride layer opposed to the substrate and containing gallium nitride as a main component thereof; and a first electrode between the gallium nitride layer and the substrate. The first electrode includes at least one hafnium layer containing a single metal of hafnium as a main component thereof, and the at least one hafnium layer is in contact with the gallium nitride layer.
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公开(公告)号:US20170272050A1
公开(公告)日:2017-09-21
申请号:US15610896
申请日:2017-06-01
Applicant: Murata Manufacturing Co., Ltd.
Inventor: Keiichi Umeda , Hiroshi Yamada , Yasuhiro Aida
CPC classification number: H03H9/02102 , B81B3/0081 , B81C2201/0181 , H03H3/0072 , H03H3/0076 , H03H9/02259 , H03H9/17 , H03H9/171 , H03H9/2463 , H03H9/2489 , H03H2009/02496 , H03H2009/241
Abstract: A method for manufacturing a resonator that effectively addresses variations in resistivity for each wafer. The method for manufacturing a resonator includes forming a Si oxide film on a surface of a degenerated Si wafer, where the Si oxide film has a thickness set that is based on the doping amount of impurity in the degenerated Si wafer.
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公开(公告)号:US11495726B2
公开(公告)日:2022-11-08
申请号:US16419219
申请日:2019-05-22
Applicant: Murata Manufacturing Co., Ltd.
Inventor: Yasuhiro Aida , Daiki Murauchi
IPC: H01L41/047 , H01L41/08 , H01L41/083 , H01L41/187 , H01L41/09 , H01L41/113
Abstract: A piezoelectric element that includes a substrate, a lower electrode layer on the substrate, an intermediate layer on the lower electrode layer, and an upper electrode layer on the intermediate layer. The intermediate layer includes a first piezoelectric layer including an aluminum nitride as a main component thereof and located between the lower electrode layer and the upper electrode layer, a first buffer layer including an aluminum nitride as a main component and located between the first piezoelectric layer and the upper electrode layer, a first intermediate electrode layer located between the first buffer layer and the upper electrode layer, and a second piezoelectric layer located between the first intermediate electrode layer and the upper electrode layer.
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公开(公告)号:US11451211B2
公开(公告)日:2022-09-20
申请号:US16126248
申请日:2018-09-10
Applicant: Murata Manufacturing Co., Ltd. , National Institute of Advanced Industrial Science and Technology
Inventor: Keiichi Umeda , Takaaki Mizuno , Yasuhiro Aida , Masato Uehara , Toshimi Nagase , Morito Akiyama
IPC: H01L41/047 , H03H9/17 , H01L41/187 , H01L41/29 , H01L41/316 , H01L41/08 , H03H3/02 , H03H9/05 , H03H9/13 , H03H9/02 , H03H9/15
Abstract: A gallium nitride structure that includes: a substrate; a gallium nitride layer opposed to the substrate and containing gallium nitride as a main component thereof; and a first electrode between the gallium nitride layer and the substrate. The first electrode includes at least one hafnium layer containing a single metal of hafnium as a main component thereof, and the at least one hafnium layer is in contact with the gallium nitride layer.
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公开(公告)号:US10965270B2
公开(公告)日:2021-03-30
申请号:US15632760
申请日:2017-06-26
Applicant: Murata Manufacturing Co., Ltd.
Inventor: Yasuhiro Aida , Keiichi Umeda
IPC: H03H9/17 , C23C14/06 , H03H9/02 , H03H9/24 , H03H9/05 , H03H3/02 , H03H9/56 , H03H9/15 , H03H3/04
Abstract: A piezoelectric film that includes crystalline AlN; at least one first element partially replacing Al in the crystalline AlN; and a second element doping the crystalline AlN and which has an ionic radius smaller than that of the first element and larger than that of Al.
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公开(公告)号:US10727807B2
公开(公告)日:2020-07-28
申请号:US15610896
申请日:2017-06-01
Applicant: Murata Manufacturing Co., Ltd.
Inventor: Keiichi Umeda , Hiroshi Yamada , Yasuhiro Aida
Abstract: A method for manufacturing a resonator that effectively addresses variations in resistivity for each wafer. The method for manufacturing a resonator includes forming a Si oxide film on a surface of a degenerated Si wafer, where the Si oxide film has a thickness set that is based on the doping amount of impurity in the degenerated Si wafer.
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