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    Apparatus for Manufacturing Reduced Iron and Method for Manufacturing the Same
    2.
    发明申请
    Apparatus for Manufacturing Reduced Iron and Method for Manufacturing the Same 有权
    制造减少铁的装置及其制造方法

    公开(公告)号：US20120174711A1

    公开(公告)日：2012-07-12

    申请号：US13496683

    申请日：2010-07-14

    申请人： Myoung-Kyun Shin ,  Dong-Won Kim ,  Sang-Hyun Kim ,  Jun-Hyuk Lee

    发明人： Myoung-Kyun Shin ,  Dong-Won Kim ,  Sang-Hyun Kim ,  Jun-Hyuk Lee

    IPC分类号： C22B5/12 ,  C22B5/14

    CPC分类号： C21B13/0033 ,  C21B13/143 ,  C21B2100/02 ,  C21B2100/06 ,  C21B2100/40 ,  C21B2100/66 ,  C21B2100/80 ,  F27D17/004

    摘要： Provided is an apparatus for manufacturing reduced iron and a method for manufacturing reduced iron. The method for manufacturing reduced iron includes the steps of: i) drying ores in an ore drier; ii) supplying the dried ores to at least one reduction reactor; iii) reducing the ores in the at least one reduction reactor and manufacturing reduced iron; iv) discharging exhaust gas by which the ores are reduced in the reduction reactor; v) branching the exhaust gas and providing the branched exhaust gas as ore feeding gas; and vi) exchanging heat between the exhaust gas and the ore feeding gas and transferring the sensible heat of the exhaust gas to the ore feeding gas. In the steps of supplying the dried ores to the at least one reduction reactor, the dried ores are supplied to the at least one reduction reactor by using the ore feeding gas.

    摘要翻译： 提供了一种制造还原铁的装置和一种制造还原铁的方法。 制造还原铁的方法包括以下步骤：i）在矿石干燥器中干燥矿石; ii）将干燥的矿石供应至至少一个还原反应器; iii）减少所述至少一个还原反应器中的矿石并制造还原铁; iv）排放还原反应器中矿石减少的废气; v）分流排气并提供分支排气作为进料气体; 和vi）在废气和送矿气体之间进行热交换，并将废气的显热转移到给矿气体。 在将干燥的矿石供应到至少一个还原反应器的步骤中，通过使用给矿气体将干燥的矿石供应至至少一个还原反应器。

    Semiconductor devices having dual trench, methods of fabricating the same, and electronic system having the same
    4.
    发明授权
    Semiconductor devices having dual trench, methods of fabricating the same, and electronic system having the same 有权
    具有双沟槽的半导体器件及其制造方法以及具有该半导体器件的电子系统

    公开(公告)号：US08519484B2

    公开(公告)日：2013-08-27

    申请号：US13368556

    申请日：2012-02-08

    申请人： Dong-Won Kim ,  Jae-Hwang Sim ,  Keon-Soo Kim ,  Young-Ho Lee

    发明人： Dong-Won Kim ,  Jae-Hwang Sim ,  Keon-Soo Kim ,  Young-Ho Lee

    IPC分类号： H01L21/70

    CPC分类号： H01L21/76229

    摘要： A semiconductor device having a dual trench and methods of fabricating the same, a semiconductor module, an electronic circuit board, and an electronic system are provided. The semiconductor device includes a semiconductor substrate having a cell region including a cell trench and a peripheral region including a peripheral trench. The cell trench is filled with a core insulating material layer, and the peripheral trench is filled with a padding insulating material layer conformably formed on an inner surface thereof and a core insulating material layer formed on an inner surface of the padding insulating material layer. The core insulating material layer has a greater fluidity than the padding insulating material layer.

    摘要翻译： 提供具有双沟槽的半导体器件及其制造方法，半导体模块，电子电路板和电子系统。 半导体器件包括具有包括单元沟道的单元区域和包括外围沟槽的周边区域的半导体衬底。 电池沟槽填充有芯绝缘材料层，并且周边沟槽填充有在内表面上顺应地形成的填充绝缘材料层和形成在填充绝缘材料层的内表面上的芯绝缘材料层。 芯绝缘材料层具有比填充绝缘材料层更大的流动性。

    Vertical channel fin field-effect transistors having increased source/drain contact area and methods for fabricating the same
    5.
    发明授权
    Vertical channel fin field-effect transistors having increased source/drain contact area and methods for fabricating the same 有权
    具有增加的源/漏接触面积的垂直沟道鳍场效应晶体管及其制造方法

    公开(公告)号：US08466511B2

    公开(公告)日：2013-06-18

    申请号：US12613025

    申请日：2009-11-05

    申请人： Chang-Woo Oh ,  Dong-Gun Park ,  Sung-Young Lee ,  Jeong-Dong Choe ,  Dong-Won Kim

    发明人： Chang-Woo Oh ,  Dong-Gun Park ,  Sung-Young Lee ,  Jeong-Dong Choe ,  Dong-Won Kim

    IPC分类号： H01L29/78

    CPC分类号： H01L29/785 ,  H01L29/66818 ,  H01L29/78618

    摘要： A fin field-effect transistor (FinFET) device includes a fin-shaped active region having first and second source/drain regions therein and a channel region therebetween vertically protruding from a semiconductor substrate. A gate electrode is formed on an upper surface and sidewalls of the channel region. First and second source/drain contacts are formed on respective upper surfaces and sidewalls of the first and second source/drain regions of the fin-shaped active region at opposite sides of the gate electrode. The channel region may be narrower than the first and second source/drain regions of the fin-shaped active region.

    摘要翻译： 翅片场效应晶体管（FinFET）器件包括其中具有第一和第二源极/漏极区域的鳍状有源区域以及从半导体衬底垂直突出的沟道区域。 栅电极形成在沟道区的上表面和侧壁上。 第一和第二源极/漏极触点形成在栅极电极的相对侧的鳍状有源区域的第一和第二源极/漏极区域的相应上表面和侧壁上。 沟道区域可以比鳍状有源区域的第一和第二源极/漏极区域窄。

    Methods of Fabricating Semiconductor Devices Having Gate Trenches
    6.
    发明申请
    Methods of Fabricating Semiconductor Devices Having Gate Trenches 审中-公开
    制造具有栅极沟槽的半导体器件的方法

    公开(公告)号：US20120238067A1

    公开(公告)日：2012-09-20

    申请号：US13422223

    申请日：2012-03-16

    申请人： Won-Cheol Jeong ,  Yun-Young Yeoh ,  Dong-Won Kim ,  Hong-Bae Park ,  Hag-Ju Cho

    发明人： Won-Cheol Jeong ,  Yun-Young Yeoh ,  Dong-Won Kim ,  Hong-Bae Park ,  Hag-Ju Cho

    IPC分类号： H01L21/336

    CPC分类号： H01L29/66545 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/78

    摘要： Methods of fabricating semiconductor devices including providing a substrate having a channel region defined therein; forming an insulation layer on the substrate; forming a gate trench for forming a gate electrode having a sidewall portion, a bottom portion and an edge portion between the sidewall portion and the bottom portion on the insulation layer, the gate electrode trench overlapping the channel region; and forming a gate electrode in the gate electrode trench. Forming the gate electrode includes forming a first metal layer pattern in the gate electrode trench and forming a second metal layer pattern on the first metal layer pattern.

    摘要翻译： 制造半导体器件的方法包括提供其中限定有沟道区的衬底; 在所述基板上形成绝缘层; 形成用于形成具有侧壁部分，底部和所述侧壁部分与所述绝缘层上的所述底部之间的边缘部分的栅电极的栅极沟槽，所述栅电极沟槽与所述沟道区重叠; 以及在所述栅电极沟槽中形成栅电极。 形成栅电极包括在栅电极沟槽中形成第一金属层图案，并在第一金属层图案上形成第二金属层图案。

    Semiconductor devices having dual trench, methods of fabricating the same, and electronic system having the same
    7.
    发明授权
    Semiconductor devices having dual trench, methods of fabricating the same, and electronic system having the same 有权
    具有双沟槽的半导体器件及其制造方法以及具有该半导体器件的电子系统

    公开(公告)号：US08129238B2

    公开(公告)日：2012-03-06

    申请号：US12951490

    申请日：2010-11-22

    申请人： Dong-Won Kim ,  Jae-Hwang Sim ,  Keon-Soo Kim ,  Young-Ho Lee

    发明人： Dong-Won Kim ,  Jae-Hwang Sim ,  Keon-Soo Kim ,  Young-Ho Lee

    IPC分类号： H01L21/8242

    CPC分类号： H01L21/76229

    摘要： A semiconductor device having a dual trench and methods of fabricating the same, a semiconductor module, an electronic circuit board, and an electronic system are provided. The semiconductor device includes a semiconductor substrate having a cell region including a cell trench and a peripheral region including a peripheral trench. The cell trench is filled with a core insulating material layer, and the peripheral trench is filled with a padding insulating material layer conformably formed on an inner surface thereof and a core insulating material layer formed on an inner surface of the padding insulating material layer. The core insulating material layer has a greater fluidity than the padding insulating material layer.

    摘要翻译： 提供具有双沟槽的半导体器件及其制造方法，半导体模块，电子电路板和电子系统。 半导体器件包括具有包括单元沟道的单元区域和包括外围沟槽的周边区域的半导体衬底。 电池沟槽填充有芯绝缘材料层，并且周边沟槽填充有在内表面上顺应地形成的填充绝缘材料层和形成在填充绝缘材料层的内表面上的芯绝缘材料层。 芯绝缘材料层具有比填充绝缘材料层更大的流动性。

    SEMICONDUCTOR DEVICES HAVING DUAL TRENCH, METHODS OF FABRICATING THE SAME, AND ELECTRONIC SYSTEM HAVING THE SAME
    8.
    发明申请
    SEMICONDUCTOR DEVICES HAVING DUAL TRENCH, METHODS OF FABRICATING THE SAME, AND ELECTRONIC SYSTEM HAVING THE SAME 有权
    具有双重TRENCH的半导体器件，其制造方法以及具有其的电子系统

    公开(公告)号：US20110165757A1

    公开(公告)日：2011-07-07

    申请号：US12951490

    申请日：2010-11-22

    申请人： Dong-Won Kim ,  Jae-Hwang Sim ,  Keon-Soo Kim ,  Young-Ho Lee

    发明人： Dong-Won Kim ,  Jae-Hwang Sim ,  Keon-Soo Kim ,  Young-Ho Lee

    IPC分类号： H01L21/762

    CPC分类号： H01L21/76229

    摘要： A semiconductor device having a dual trench and methods of fabricating the same, a semiconductor module, an electronic circuit board, and an electronic system are provided. The semiconductor device includes a semiconductor substrate having a cell region including a cell trench and a peripheral region including a peripheral trench. The cell trench is filled with a core insulating material layer, and the peripheral trench is filled with a padding insulating material layer conformably formed on an inner surface thereof and a core insulating material layer formed on an inner surface of the padding insulating material layer. The core insulating material layer has a greater fluidity than the padding insulating material layer.

    摘要翻译： 提供具有双沟槽的半导体器件及其制造方法，半导体模块，电子电路板和电子系统。 半导体器件包括具有包括单元沟道的单元区域和包括外围沟槽的周边区域的半导体衬底。 电池沟槽填充有芯绝缘材料层，并且周边沟槽填充有在内表面上顺应地形成的填充绝缘材料层和形成在填充绝缘材料层的内表面上的芯绝缘材料层。 芯绝缘材料层具有比填充绝缘材料层更大的流动性。

    Electromechanical memory devices and methods of manufacturing the same
    9.
    发明授权
    Electromechanical memory devices and methods of manufacturing the same 有权
    机电存储器件及其制造方法

    公开(公告)号：US07947558B2

    公开(公告)日：2011-05-24

    申请号：US12720276

    申请日：2010-03-09

    申请人： Eunjung Yun ,  Sung-Young Lee ,  Dong-Won Kim

    发明人： Eunjung Yun ,  Sung-Young Lee ,  Dong-Won Kim

    IPC分类号： H01L21/336

    CPC分类号： H01L27/10 ,  H01L2924/0002 ,  H01L2924/00

    摘要： In a memory device and a method of forming the same, in one embodiment, the memory device comprises a first word line structure on a substrate, the first word line structure extending in a first direction. A bit line is provided over the first word line structure and spaced apart from the first word line by a first gap, the bit line extending in a second direction transverse to the first direction. A second word line structure is provided over the bit line and spaced apart from the bit line by a second gap, the second word line structure extending in the first direction. The bit line is suspended between the first word line structure and the second word line structure such that the bit line deflects to be electrically coupled with a top portion of the first word line structure through the first gap in a first bent position and deflects to be electrically coupled with a bottom portion of the second word line structure through the second gap in a second bent position, and is isolated from the first word line structure and the second word line structure in a rest position.

    摘要翻译： 在一种存储器件及其形成方法中，在一个实施例中，存储器件包括在衬底上的第一字线结构，第一字线结构沿第一方向延伸。 位线设置在第一字线结构之上并且与第一字线间隔开第一间隙，位线沿横向于第一方向的第二方向延伸。 第二字线结构设置在位线上并与位线间隔第二间隙，第二字线结构沿第一方向延伸。 位线悬挂在第一字线结构和第二字线结构之间，使得位线在第一弯曲位置通过第一间隙偏转以与第一字线结构的顶部电耦合，并且偏转为 在第二弯曲位置通过第二间隙与第二字线结构的底部电耦合，并且在静止位置与第一字线结构和第二字线结构隔离。

    Gate-all-around type semiconductor device and method of manufacturing the same
    10.
    发明申请
    Gate-all-around type semiconductor device and method of manufacturing the same 有权
    栅极全周型半导体器件及其制造方法

    公开(公告)号：US20100314604A1

    公开(公告)日：2010-12-16

    申请号：US12805776

    申请日：2010-08-19

    申请人： Sung-Dae Suk ,  Dong-Won Kim ,  Kyoung-Hwan Yeo

    发明人： Sung-Dae Suk ,  Dong-Won Kim ,  Kyoung-Hwan Yeo

    IPC分类号： H01L29/775

    CPC分类号： H01L29/78696 ,  B82Y10/00 ,  H01L29/0665 ,  H01L29/0673 ,  H01L29/42392

    摘要： The gate-all-around (GAA) type semiconductor device may include source/drain layers, a nanowire channel, a gate electrode and an insulation layer pattern. The source/drain layers may be disposed at a distance in a first direction on a semiconductor substrate. The nanowire channel may connect the source/drain layers. The gate electrode may extend in a second direction substantially perpendicular to the first direction. The gate electrode may have a height in a third direction substantially perpendicular to the first and second directions and may partially surround the nanowire channel. The insulation layer pattern may be formed between and around the source/drain layers on the semiconductor substrate and may cover the nanowire channel and a portion of the gate electrode. Thus, a size of the gate electrode may be reduced, and/or a gate induced drain leakage (GIDL) and/or a gate leakage current may be reduced.

    摘要翻译： 栅极全能（GAA）型半导体器件可以包括源极/漏极层，纳米线沟道，栅电极和绝缘层图案。 源极/漏极层可以在半导体衬底上沿第一方向设置一定距离。 纳米线通道可以连接源极/漏极层。 栅电极可以在基本上垂直于第一方向的第二方向上延伸。 栅电极可以具有基本上垂直于第一和第二方向的第三方向的高度，并且可以部分地包围纳米线通道。 绝缘层图案可以形成在半导体衬底上的源极/漏极层之间和周围，并且可以覆盖纳米线沟道和栅电极的一部分。 因此，可以减小栅电极的尺寸，和/或栅极感应漏极泄漏（GIDL）和/或栅极泄漏电流可能降低。