-
公开(公告)号：US20190333998A1
公开(公告)日：2019-10-31
申请号：US16224882
申请日：2018-12-19
Inventor： Keiko MASUMOTO , Takashi MITANI , Kazuma ETO , Kazutoshi KOJIMA , Tomohisa KATO
Abstract: A high quality silicon carbide epitaxial wafer using a p-type silicon carbide single crystal substrate of low resistivity. The silicon carbide epitaxial wafer includes a p-type 4H—SiC single crystal substrate that has a first main surface having an off angle with respect to (0001) plane, and has a resistivity of less than 0.4 Ωcm, and a silicon carbide epitaxial layer that is disposed on the first main surface of the p-type 4H—SiC single crystal substrate, in which an off direction of the off angle is the direction.
-
2.发明申请Silicon Carbide Epitaxial Wafer, Method for Manufacturing Silicon Carbide Epitaxial Wafer, Device for Manufacturing Silicon Carbide Epitaxial Wafer, and Silicon Carbide Semiconductor Element 有权碳化硅外延晶片，用于制造碳化硅外延晶片的方法，用于制造碳化硅外延晶片的装置和碳化硅半导体元件公开(公告)号：US20160168751A1
公开(公告)日：2016-06-16
申请号：US14778271
申请日：2014-02-20
Inventor： Keiko MASUMOTO , Kazutoshi KOJIMA , Kentaro TAMURA
CPC classification number: C30B25/186 , C30B25/20 , C30B29/36 , H01L21/02378 , H01L21/02433 , H01L21/02529 , H01L21/0262 , H01L21/02658 , H01L21/0475 , H01L21/3065 , H01L28/00 , H01L29/04 , H01L29/045 , H01L29/1608
Abstract: To provide silicon carbide epitaxial wafer in which occurrence of giant step bunchings (GSBs) caused by basal plane dislocations (BPDs) that occur during hydrogen etching is suppressed on low off-angle silicon carbide substrate to decrease surface defect density of epitaxially grown layer to allow formation of silicon carbide semiconductor device having high reliability, method for manufacturing the wafer, and apparatus for manufacturing the wafer, and silicon carbide semiconductor device having the wafer.A silicon carbide epitaxial wafer of the present invention is such that epitaxially grown layer is disposed on silicon carbide substrate which has α-type crystal structure and in which (0001) Si face is tilted at greater than 0° and less than 5°, wherein surface defect density of the epitaxially grown layer based on giant step bunching caused by basal plane dislocation on substrate surface of the silicon carbide substrate is ≦20/cm2.
Abstract translation: 为了提供碳化硅外延晶片，其中在低偏角碳化硅衬底处抑制在氢蚀刻期间发生的由基底面位错（BPD）引起的巨大步长束（GSB）的发生，以降低外延生长层的表面缺陷密度，以允许 具有高可靠性的碳化硅半导体器件的制造，晶片的制造方法以及晶片的制造装置以及具有晶片的碳化硅半导体器件。 本发明的碳化硅外延晶片是这样的：外延生长层设置在具有α型晶体结构的碳化硅衬底中，其中（0001）Si面倾斜大于0°且小于5°，其中 基于在碳化硅衬底的衬底表面上的基面位错引起的巨大步骤聚集的外延生长层的表面缺陷密度为20 / cm2。
-
公开(公告)号：US20240332281A1
公开(公告)日：2024-10-03
申请号：US18737031
申请日：2024-06-07
Inventor： Akira NAKAJIMA , Shinsuke HARADA , Kazutoshi KOJIMA
IPC: H01L27/02 , H01L29/20 , H01L29/778
CPC classification number: H01L27/0255 , H01L29/2003 , H01L29/7786
Abstract: A destructive breakdown mode that leads to the destruction of a device is suppressed, in the case where a gallium nitride-based high electron mobility transistor is used as a power device. A diode is connected in antiparallel to a HEMT, and this antiparallel connected diode is designed such that an avalanche breakdown occurs therein before the drain-source voltage, which is the difference between the drain potential applied to a drain electrode and the source potential applied to a source electrode, exceeds the withstand voltage of the HEMT.
-
公开(公告)号：US20190273136A1
公开(公告)日：2019-09-05
申请号：US16280083
申请日：2019-02-20
Inventor： Keiko MASUMOTO , Satoshi SEGAWA , Kazutoshi KOJIMA , Tomohisa KATO , Toshiyuki OHNO
Abstract: A silicon carbide epitaxial wafer (10) of the present invention is a silicon carbide epitaxial wafer including: a silicon carbide substrate (1) and a silicon carbide layer (2) provided on a first principal plane (1A) of the silicon carbide substrate (1) and having a film thickness of 100 μm or more, wherein a warpage amount of the silicon carbide epitaxial wafer is −20 μm or more and 20 μm or less.
-
-
-
Search Results
4
records
(took 0.019 seconds)
