WIRING SUBSTRATE
    1.
    发明公开
    WIRING SUBSTRATE 审中-公开

    公开(公告)号:US20230299011A1

    公开(公告)日:2023-09-21

    申请号:US18183250

    申请日:2023-03-14

    Inventor: Takahiro HAYASHI

    CPC classification number: H01L23/544 B32B15/20

    Abstract: Disclosed is a wiring substrate whose orientation can be easily recognized and which can prevent occurrence of a failure which would otherwise occur after a semiconductor device is mounted on the wiring substrate, or after an electronic component composed of the wiring substrate and the semiconductor device mounted thereon is mounted on a base substrate or the like. The wiring substrate includes a base substrate, and a metallic member disposed on a first face of the base substrate. The metallic member has a shape which is plane symmetric with respect to a plane which extends through a center of the first face and is perpendicular to the first face. A recess is formed, as a partial dent, on one of outer surfaces of the metallic member.

    WIRING SUBSTRATE
    2.
    发明申请
    WIRING SUBSTRATE 审中-公开

    公开(公告)号:US20200029431A1

    公开(公告)日:2020-01-23

    申请号:US16504673

    申请日:2019-07-08

    Inventor: Takahiro HAYASHI

    Abstract: A wiring substrate has a substrate body formed by a single or a plurality of insulating layers and having front and back surfaces located at opposite sides of the substrate body; a plurality of pads formed on at least one of the front surface, the back surface and an inner layer surface that is located between the front and back surfaces, and having a staggered arrangement in plan view; and a plurality of via conductors formed at each of the pads, extending in a thickness direction of the substrate body with the plurality of via conductors being parallel to each other and connecting the pads located on different surfaces. Arrangement, in plan view, of the plurality of via conductors connecting to the pad and arrangement, in plan view, of the plurality of via conductors connecting to an adjacent pad located on the same surface are different from each other.

    WIRING SUBSTRATE AND METHOD FOR PRODUCING WIRING SUBSTRATE
    3.
    发明申请
    WIRING SUBSTRATE AND METHOD FOR PRODUCING WIRING SUBSTRATE 有权
    接线基板及其制造方法

    公开(公告)号:US20140318846A1

    公开(公告)日:2014-10-30

    申请号:US14258984

    申请日:2014-04-22

    Abstract: A wiring substrate includes a layered structure including one or more insulating layers and one or more conductor layers; a plurality of connection terminals formed on the layered structure; a first resin layer formed on the layered structure and having (defining) a plurality of first openings through which the connection terminals are respectively exposed; and a second resin layer formed on the first resin layer and having (defining) a plurality of second openings through which the connection terminals are respectively exposed and which are smaller in opening diameter than the first openings, wherein the second resin layer has, around each of the second openings, an inclined surface which is formed such that the distance between the inclined surface and the layered structure decreases toward the second opening.

    Abstract translation: 布线基板包括层叠结构,其包括一个或多个绝缘层和一个或多个导体层; 形成在层状结构上的多个连接端子; 形成在所述层状结构上并具有(限定)所述连接端子分别暴露的多个第一开口的第一树脂层; 以及形成在第一树脂层上并具有(限定)多个第二开口的第二树脂层,连接端子分别通过该开口分别露出,并且开口直径小于第一开口,其中第二树脂层在每个 第二开口的倾斜表面形成为使得倾斜表面和层状结构之间的距离朝向第二开口减小。

    WIRING SUBSTRATE AND METHOD FOR PRODUCING THE SAME
    4.
    发明申请
    WIRING SUBSTRATE AND METHOD FOR PRODUCING THE SAME 审中-公开
    配线基板及其制造方法

    公开(公告)号:US20140097007A1

    公开(公告)日:2014-04-10

    申请号:US14037496

    申请日:2013-09-26

    Abstract: Embodiments of the present wiring substrate include a stacked body including one or more insulation layers and one or more conductive layers, wherein the wiring substrate has a plurality of connection terminals formed on the stacked body, each connection terminal has a top surface whose area is smaller than that of each of opposite side surfaces thereof, and a filling member provided in a filling manner between the connection terminals. The top surface of each connection terminal has an area larger than that of a portion of each side surfaces portion exposed from the filling member, and a bonding layer containing a solder is formed on the top surface.

    Abstract translation: 本发明的布线基板的具体实施方式包括具有一个以上的绝缘层和一个以上的导电层的层叠体,其中,布线基板具有形成在层叠体上的多个连接端子,各连接端子的面积较小的顶面 比其各个相对侧面的填充构件和填充构件设置在连接端子之间。 每个连接端子的顶表面的面积大于从填充构件露出的每个侧表面部分的部分的面积,并且在顶表面上形成包含焊料的接合层。

    WIRING SUBSTRATE
    6.
    发明申请
    WIRING SUBSTRATE 审中-公开
    接线基板

    公开(公告)号:US20150357277A1

    公开(公告)日:2015-12-10

    申请号:US14762185

    申请日:2013-12-12

    Abstract: To provide a wiring substrate which can reliably prevent progress of cracking in a solder bump, and which exhibits improved reliability. The wiring substrate 10 of the present invention includes a substrate main body 11, pads 61, and a solder resist 81. The pads 61 are provided on the substrate back surface 13 of the substrate main body, and have surfaces 62 on which solder bumps 84 employed for connection of a motherboard 91 can be formed. The solder resist 81 covers the substrate back surface 13 of the substrate main body, and has openings 82 through which the pads 61 are exposed. A protrusion 71 is formed on a portion of the surface 62 of each pad 61. The height A4 of the end surface 72 of the protrusion 71, as measured from the surface 62 of the pad 61, is smaller than the depth of each opening 82. The protrusion 71 is provided in the opening 82 such that the peripheral surface 73 of the protrusion 71 faces the inner surface of the opening 82, and the protrusion 71 has a plan-view shape similar to that of the opening 82.

    Abstract translation: 提供一种可以可靠地防止焊料凸块的开裂进行的布线基板,其可靠性提高。 本发明的布线基板10包括基板主体11,焊盘61和阻焊剂81.焊盘61设置在基板主体的基板背面13上,并且具有表面62,焊料凸块84 用于连接主板91可以形成。 阻焊剂81覆盖基板主体的基板背面13,并且具有开口82,焊盘61通过该开口82露出。 在每个垫61的表面62的一部分上形成突起71.突起71的端面72的高度A4,从垫61的表面62测量,小于每个开口82的深度 突起71设置在开口82中,使得突起71的周面73面对开口82的内表面,突起71具有与开口82相似的平面形状。

    METHOD OF MANUFACTURING WIRING SUBSTRATE, AND WIRING SUBSTRATE
    7.
    发明申请
    METHOD OF MANUFACTURING WIRING SUBSTRATE, AND WIRING SUBSTRATE 有权
    制造接线基板和接线基板的方法

    公开(公告)号:US20150334850A1

    公开(公告)日:2015-11-19

    申请号:US14707295

    申请日:2015-05-08

    Inventor: Takahiro HAYASHI

    Abstract: A method of manufacturing a wiring substrate according to the present invention includes a step of forming a wiring layer including connection terminals on a first insulating layer; a step of forming a second insulating layer on the wiring layer and on the first insulating layer; a step of forming electrically insulative dummy portions separated from the wiring layer on the first insulating layer through patterning of the second insulating layer; a step of forming a third insulating layer on the wiring layer, on the dummy portions, and on the first insulating layer; and a step of forming openings in the third insulating layer for exposing the connection terminals in such a manner that upper end portions of the connection terminals protrude from the third insulating layer, and lower end portions of the connection terminals are embedded in the third insulating layer.

    Abstract translation: 根据本发明的制造布线基板的方法包括在第一绝缘层上形成包括连接端子的布线层的步骤; 在所述布线层和所述第一绝缘层上形成第二绝缘层的步骤; 通过图案化所述第二绝缘层而形成与所述第一绝缘层上的所述布线层分离的电绝缘的虚设部分的步骤; 在所述布线层上,所述虚拟部分上和所述第一绝缘层上形成第三绝缘层的步骤; 以及在所述第三绝缘层中形成用于暴露所述连接端子的开口的步骤,使得所述连接端子的上端部从所述第三绝缘层突出,并且所述连接端子的下端部嵌入所述第三绝缘层 。

    WIRING SUBSTRATE AND METHOD OF MANUFACTURING THE SAME
    8.
    发明申请
    WIRING SUBSTRATE AND METHOD OF MANUFACTURING THE SAME 审中-公开
    接线基板及其制造方法

    公开(公告)号:US20130081862A1

    公开(公告)日:2013-04-04

    申请号:US13633421

    申请日:2012-10-02

    Abstract: Embodiments of the present invention provide a wiring substrate which is excellent in terms of the reliability of connection between the wiring substrate and a semiconductor chip. In some embodiments the wiring substrate comprises a first build-up layer in which resin insulation layers and conductor layers are laminated alternately. The outermost conductor layer can include a plurality of connection terminal portions to which a semiconductor chip is flip-chip connected. The plurality of connection terminal portions can be exposed through openings of a solder resist layer. Each of the connection terminal portions includes a connection region to which a connection terminal of the semiconductor chip is to be connected, and a wiring region which extends in a planar direction from the connection region and which is narrower than the connection region. The surface of the wiring region has a solder wettability lower than that of the surface of the connection region.

    Abstract translation: 本发明的实施例提供了一种在布线基板和半导体芯片之间的连接可靠性方面优异的布线基板。 在一些实施例中,布线基板包括交替层叠树脂绝缘层和导体层的第一堆积层。 最外面的导体层可以包括半导体芯片倒装芯片连接的多个连接端子部分。 多个连接端子部分可以通过阻焊层的开口露出。 每个连接端子部分包括连接半导体芯片的连接端子的连接区域和从连接区域在平面方向上延伸并且比连接区域窄的布线区域。 布线区域的表面的焊料润湿性低于连接区域的表面。

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