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    Computer motherboard with a control chip having specific pin arrangement for fast cache access
    3.
    发明授权
    Computer motherboard with a control chip having specific pin arrangement for fast cache access 有权
    具有控制芯片的计算机主板具有特定的引脚布置，用于快速缓存访问

    公开(公告)号：US6134701A

    公开(公告)日：2000-10-17

    申请号：US159441

    申请日：1998-09-22

    申请人： Shu-Hui Chen ,  Tsai-Sheng Chen ,  Nai-Shung Chang

    发明人： Shu-Hui Chen ,  Tsai-Sheng Chen ,  Nai-Shung Chang

    IPC分类号： G06F12/08 ,  H05K1/18 ,  G06F3/00

    CPC分类号： H05K1/181 ,  G06F12/0893 ,  H05K2201/09227 ,  H05K2201/10689 ,  H05K2201/10734 ,  Y02P70/611

    摘要： The present invention provides a computer motherboard having an Intel P54C compatible processor socket and a control chip having specifically arranged data pins and address pins which allows a short signal path arrangement from the processor socket to a cache tap RAM and a cache data RAM. The computer motherboard comprises a four-layer printed circuit board, a processor socket, a cache data RAM, a cache tag RAM, and a control chip. All these components are connected by using a high-order-bit data bus, a low-order-bit data bus, and an address bus through the top and bottom layers of the circuit board. The cache data RAM is positioned on the right side of the processor socket. The control chip is positioned on the top side of the cache data RAM and on the top-right side of the processor socket. It comprises an address section positioned at a bottom-middle portion of the control chip, a high-order-bit data section positioned at a bottom-right corner of the control chip, and a low-order-bit data section positioned at a bottom-left corner of the control chip. The cache tag RAM is positioned between the processor socket and the cache data RAM.

    摘要翻译： 本发明提供了一种具有Intel P54C兼容处理器插座的计算机主板和具有特别布置的数据引脚和地址引脚的控制芯片，其允许从处理器插槽到高速缓存分接器RAM和高速缓存数据RAM的短信号路径布置。 计算机主板包括四层印刷电路板，处理器插座，高速缓存数据RAM，高速缓存标签RAM和控制芯片。 所有这些组件通过使用高位数据总线，低位数据总线和通过电路板的顶层和底层的地址总线连接。 缓存数据RAM位于处理器插槽的右侧。 控制芯片位于高速缓存数据RAM的顶侧，并位于处理器插槽的右上侧。 它包括位于控制芯片的底部中间部分的地址部分，位于控制芯片的右下角的高位数据部分和位于底部的低位数据部分 - 控制芯片的左角。 高速缓存标签RAM位于处理器插槽和高速缓存数据RAM之间。

    Layout structure and method for supporting two different package techniques of CPU
    4.
    发明授权
    Layout structure and method for supporting two different package techniques of CPU 有权
    支持CPU的两种不同封装技术的布局结构和方法

    公开(公告)号：US06794744B2

    公开(公告)日：2004-09-21

    申请号：US10064426

    申请日：2002-07-12

    申请人： Nai-Shung Chang ,  Tsai-Sheng Chen ,  Shu-Hui Chen

    发明人： Nai-Shung Chang ,  Tsai-Sheng Chen ,  Shu-Hui Chen

    IPC分类号： H01L2352

    CPC分类号： H05K1/0295 ,  H05K1/0298 ,  H05K1/18 ,  H05K2201/09345 ,  H05K2201/09954 ,  H05K2201/10522 ,  H05K2201/10704 ,  H05K2201/10734

    摘要： A layout structure of a central processing unit (CPU) that supports two different package techniques, having a motherboard that comprising the layout structure and a layout method. The layout structure of the preferred embodiment according to the present invention from up to down sequentially placed a top signal layer, a grounded layer, a power layer having an operating potential area and a grounded potential area, and a bottom solder layer in the area where the signals of the CPU are coupled to the signals of the control chip, so that the signals that are placed on the bottom solder layer can refer to a grounded potential area of the power layer.

    摘要翻译： 中央处理单元（CPU）的布局结构，其支持两种不同的封装技术，具有包括布局结构的主板和布局方法。 根据本发明的优选实施例的布局结构从上到下顺序地放置了顶部信号层，接地层，具有工作电位区域的功率层和接地电位区域，以及底部焊料层， CPU的信号耦合到控制芯片的信号，使得放置在底部焊料层上的信号可以指功率层的接地电位区域。

    Layout structure and method for supporting two different package techniques of CPU
    5.
    发明授权
    Layout structure and method for supporting two different package techniques of CPU 有权
    支持CPU的两种不同封装技术的布局结构和方法

    公开(公告)号：US06888071B2

    公开(公告)日：2005-05-03

    申请号：US10710731

    申请日：2004-07-30

    申请人： Nai-Shung Chang ,  Tsai-Sheng Chen ,  Shu-Hui Chen

    发明人： Nai-Shung Chang ,  Tsai-Sheng Chen ,  Shu-Hui Chen

    IPC分类号： H05K1/00 ,  H05K1/18 ,  H05K1/03

    CPC分类号： H05K1/0295 ,  H05K1/0298 ,  H05K1/18 ,  H05K2201/09345 ,  H05K2201/09954 ,  H05K2201/10522 ,  H05K2201/10704 ,  H05K2201/10734

    摘要： A layout structure of a central processing unit (CPU) that supports two different package techniques, comprising a motherboard that comprises the layout structure and a layout method. The layout structure of the preferred embodiment according to the present invention from up to down sequentially places a top signal layer, a grounded layer, a power layer having a grounded potential, and a bottom solder layer in the area where the signals of the CPU are coupled to the signals of the control chip, so that the signals that are placed on the bottom solder layer can refer to a grounded potential area of the power layer. Therefore, part of signals of the CPU that are coupled to the control chip can be placed on the bottom solder layer. Since the preferred embodiment of the present invention provides more flexibility in the placement design, a layout structure that supports the Pentium IV CPUs of different package techniques can be designed on the motherboard of the 4 layers stack structure, and these two CPUs can be supported by the same control chip.

    摘要翻译： 支持两种不同包装技术的中央处理单元（CPU）的布局结构，包括包括布局结构和布局方法的主板。 根据本发明的优选实施例的布局结构从上到下顺序地在CPU的信号区域中放置顶层信号层，接地层，具有接地电位的功率层和底部焊料层 耦合到控制芯片的信号，使得放置在底部焊料层上的信号可以指功率层的接地电位区域。 因此，耦合到控制芯片的CPU的部分信号可以放置在底部焊料层上。 由于本发明的优选实施例在布局设计中提供了更多的灵活性，因此可以在四层堆栈结构的主板上设计支持不同封装技术的Pentium IV CPU的布局结构，并且这两个CPU可以被 相同的控制芯片。

    Chipset supporting multiple CPU's and layout method thereof
    6.
    发明授权
    Chipset supporting multiple CPU's and layout method thereof 有权
    支持多CPU的芯片组及其布局方法

    公开(公告)号：US06877102B2

    公开(公告)日：2005-04-05

    申请号：US10013983

    申请日：2001-12-10

    申请人： Nai-Shung Chang ,  Tsai-Sheng Chen ,  Shu-Hui Chen

    发明人： Nai-Shung Chang ,  Tsai-Sheng Chen ,  Shu-Hui Chen

    IPC分类号： G06F13/40 ,  G06F1/04

    CPC分类号： G06F13/4068

    摘要： A chipset to support multiple CPU's and a layout method thereof. Those independent signal lines for delivering high frequency clock signals of the chipset are isolated from using by other signals without being multiplexed. Trace length of the independent signal line is shorter than that of the others. The spaces between the independent signal line and others are also larger than that between other signal lines. Signal transmission quality is significantly upgraded because the high frequency clock signal is not multiplexed and isolated from others.

    摘要翻译： 支持多CPU的芯片组及其布局方法。 用于传送芯片组的高频时钟信号的这些独立信号线与其他信号的使用隔离而不被复用。 独立信号线的跟踪长度短于其他信号线。 独立信号线与其他信号线之间的空间也大于其他信号线之间的间隔。 信号传输质量显着升高，因为高频时钟信号不被复用并与其隔离。

    Memory control system for controlling write-enable signals
    7.
    发明授权
    Memory control system for controlling write-enable signals 有权
    用于控制写使能信号的存储器控​​制系统

    公开(公告)号：US06377510B2

    公开(公告)日：2002-04-23

    申请号：US09756586

    申请日：2001-01-09

    申请人： Nai-Shung Chang ,  Tsai-Sheng Chen ,  Shu-Hui Chen

    发明人： Nai-Shung Chang ,  Tsai-Sheng Chen ,  Shu-Hui Chen

    IPC分类号： G11C700

    CPC分类号： G06F13/1694

    摘要： A memory control system for controlling write-enable signals. The memory control system has a first memory slot having a write-enable pin thereon, a second memory slot having a first write-enable pin and a second write-enable pin thereon and a control chipset having a write-enable pin and a dual-purpose write-enable/memory-parity-data pin thereon. The write-enable pin of the control chipset is connected to the write-enable pin of the first memory slot and the first write-enable pin of the second memory slot. The write-enable/memory-parity-data pin of the control chipset is connected to the second write-enable pin of the second memory slot. In this invention, since the design of the write-enable system is more flexible, length of trace line on a computer board can be greatly reduced. In addition, the system permits the incorporation of one cycle (1T) timing into design of memory access commands.

    摘要翻译： 一种用于控制写使能信号的存储器控​​制系统。 存储器控制系统具有在其上具有写使能引脚的第一存储器插槽，其上具有第一写使能引脚和第二写使能引脚的第二存储器插槽以及具有写使能引脚和双引脚引脚的控制芯片组， 目的写入/存储器奇偶校验数据引脚。 控制芯片组的写使能引脚连接到第一存储器插槽的写使能引脚和第二存储器插槽的第一写使能引脚。 控制芯片组的写使能/存储器奇偶校验数据引脚连接到第二存储器插槽的第二写使能引脚。 在本发明中，由于写使能系统的设计更灵活，所以可以大大减少计算机板上的迹线长度。 此外，该系统允许将一个周期（1T）定时并入到存储器访问命令的设计中。

    METHOD FOR REDUCING POWER CONSUMPTION OF A COMPUTER SYSTEM IN THE WORKING STATE
    8.
    发明申请
    METHOD FOR REDUCING POWER CONSUMPTION OF A COMPUTER SYSTEM IN THE WORKING STATE 有权
    降低工作状态下计算机系统功耗的方法

    公开(公告)号：US20070288782A1

    公开(公告)日：2007-12-13

    申请号：US11423722

    申请日：2006-06-13

    申请人： Nai-Shung Chang ,  Chia-Hsing Yu

    发明人： Nai-Shung Chang ,  Chia-Hsing Yu

    IPC分类号： G06F1/00

    CPC分类号： G06F1/324 ,  G06F1/3225 ,  G06F1/3296 ,  Y02D10/126 ,  Y02D10/172

    摘要： A method for reducing power consumption of a computer system in a working state is provided. The computer system comprises a processor, a memory and a chipset, and the processor is connected with the chipset through a processor bus. The method comprises classifying the power saving level of the computer system into a predetermined number of power saving modes, checking at least one power saving mode transition condition to determine whether to automatically raise the power saving mode of the computer system, and raising the power saving mode of the computer system by lowering a first voltage supply level of the chipset and a second voltage supply level of the memory and decreasing a first working frequency of the processor bus and a second working frequency of the memory. The power consumption of the computer system is further reduced in comparison with a normal working state when the power saving mode of the computer system is further raised.

    摘要翻译： 提供了一种降低处于工作状态的计算机系统的功耗的方法。 计算机系统包括处理器，存储器和芯片组，并且处理器通过处理器总线与芯片组连接。 该方法包括将计算机系统的省电水平分为预定数量的省电模式，检查至少一个省电模式转换条件，以确定是否自动提高计算机系统的省电模式，并提高节电 通过降低芯片组的第一电压供应电平和存储器的第二电压供应电平并降低处理器总线的第一工作频率和存储器的第二工作频率来实现计算机系统的模式。 当计算机系统的省电模式进一步提高时，与正常工作状态相比，计算机系统的功耗进一步降低。

    Power controller and associated multi-processor type supporting computer system
    9.
    发明授权
    Power controller and associated multi-processor type supporting computer system 有权
    电源控制器和相关的多处理器类型支持计算机系统

    公开(公告)号：US06944783B2

    公开(公告)日：2005-09-13

    申请号：US10037896

    申请日：2001-10-22

    申请人： Chia-Hsing Yu ,  Nai-Shung Chang

    发明人： Chia-Hsing Yu ,  Nai-Shung Chang

    IPC分类号： G06F1/26

    CPC分类号： G06F1/26

    摘要： A power controller for a computer system capable of supporting multiple processor types. The power controller receives a voltage identification signal from the microprocessor and a microprocessor selection signal from a motherboard to provide a correct voltage specification signal and terminal voltage to the microprocessor. The invention also provides voltage specification signals and terminal voltages to the motherboard of a computer system that can support a multiple of processor types.

    摘要翻译： 一种能够支持多种处理器类型的计算机系统的电源控制器。 功率控制器接收来自微处理器的电压识别信号和来自母板的微处理器选择信号，以向微处理器提供正确的电压指定信号和端电压。 本发明还向可以支持多种处理器类型的计算机系统的主板提供电压指定信号和端电压。

    Method for reducing power consumption of a computer system in the working state
    10.
    发明授权
    Method for reducing power consumption of a computer system in the working state 有权
    降低工作状态下计算机系统功耗的方法

    公开(公告)号：US08335941B2

    公开(公告)日：2012-12-18

    申请号：US12752201

    申请日：2010-04-01

    申请人： Nai-Shung Chang ,  Chia-Hsing Yu

    发明人： Nai-Shung Chang ,  Chia-Hsing Yu

    IPC分类号： G06F1/04 ,  G06F1/12 ,  G06F5/06

    CPC分类号： G06F1/324 ,  G06F1/3225 ,  G06F1/3296 ,  Y02D10/126 ,  Y02D10/172

    摘要： A method for reducing power consumption of a computer system in a working state is provided. The computer system comprises a processor, a memory and a chipset, and the processor is connected with the chipset through a processor bus. The method comprises classifying the power saving level of the computer system into a predetermined number of power saving modes, checking at least one power saving mode transition condition to determine whether to automatically raise the power saving mode of the computer system, and raising the power saving mode of the computer system by lowering a first voltage supply level of the chipset and a second voltage supply level of the memory and decreasing a first working frequency of the processor bus and a second working frequency of the memory. The power consumption of the computer system is further reduced in comparison with a normal working state when the power saving mode of the computer system is further raised.

    摘要翻译： 提供了一种降低处于工作状态的计算机系统的功耗的方法。 计算机系统包括处理器，存储器和芯片组，并且处理器通过处理器总线与芯片组连接。 该方法包括将计算机系统的省电水平分为预定数量的省电模式，检查至少一个省电模式转换条件，以确定是否自动提高计算机系统的省电模式，并提高节电 通过降低芯片组的第一电压供应电平和存储器的第二电压供应电平并降低处理器总线的第一工作频率和存储器的第二工作频率来实现计算机系统的模式。 当计算机系统的省电模式进一步提高时，与正常工作状态相比，计算机系统的功耗进一步降低。