公开(公告)号：US06946731B2

公开(公告)日：2005-09-20

申请号：US10173231

申请日：2002-06-14

申请人： Nai-Shung Chang ,  Shu-Hui Chen ,  Tsai-Sheng Chen ,  Chia-Hsing Yu

发明人： Nai-Shung Chang ,  Shu-Hui Chen ,  Tsai-Sheng Chen ,  Chia-Hsing Yu

IPC分类号： H01L23/34 ,  H01L23/48 ,  H01L23/498 ,  H01L23/50 ,  H01L23/52 ,  H01L29/00 ,  H01L31/00 ,  H05K1/11 ,  H05K1/18

CPC分类号： H01L23/49838 ,  H01L23/50 ,  H01L24/48 ,  H01L2224/05599 ,  H01L2224/45099 ,  H01L2224/48227 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19105 ,  H01L2924/30107 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2924/00012

摘要： This invention relates to a layout structure for providing stable power supply to a four-layer motherboard and a main bridge chip substrate. In the invention, on the top signal layer and power path of the bottom solder layer for layout of the main bridge chip and on the power ring, the decoupling capacitors are connected in between the ground bonding pads/solder balls and the power bonding pads/solder balls of the power paths and power rings, so as to provide a stable power supply for the operation of the main bridge chip. In this invention, the ground bonding pad/solder ball connected with each power bonding pad/solder ball can be the closest ground bonding pad/solder ball to the power bonding pad/solder ball. In addition, in the embodiment of the main bridge chip substrate, decoupling capacitors can be disposed at four corners of the power ring or underneath the bonding wires, or can be packaged inside the molding compound.

公开(公告)号：US20050263849A1

公开(公告)日：2005-12-01

申请号：US11196039

申请日：2005-08-02

申请人： Nai-Shung Chang ,  Shu-Hui Chen ,  Tsai-Sheng Chen ,  Chia-Hsing Yu

发明人： Nai-Shung Chang ,  Shu-Hui Chen ,  Tsai-Sheng Chen ,  Chia-Hsing Yu

IPC分类号： H01L23/34 ,  H01L23/48 ,  H01L23/498 ,  H01L23/50 ,  H01L23/52 ,  H01L29/00 ,  H01L31/00 ,  H05K1/11 ,  H05K1/18

CPC分类号： H01L23/49838 ,  H01L23/50 ,  H01L24/48 ,  H01L2224/05599 ,  H01L2224/45099 ,  H01L2224/48227 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19105 ,  H01L2924/30107 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2924/00012

摘要： This invention relates to a layout structure for providing stable power supply to a four-layer motherboard and a main bridge chip substrate. In the invention, on the top signal layer and power path of the bottom solder layer for layout of the main bridge chip and on the power ring, the decoupling capacitors are connected in between the ground bonding pads/solder balls and the power bonding pads/solder balls of the power paths and power rings, so as to provide a stable power supply for the operation of the main bridge chip. In this invention, the ground bonding pad/solder ball connected with each power bonding pad/solder ball can be the closest ground bonding pad/solder ball to the power bonding pad/solder ball. In addition, in the embodiment of the main bridge chip substrate, decoupling capacitors can be disposed at four corners of the power ring or underneath the bonding wires, or can be packaged inside the molding compound.

摘要翻译： 本发明涉及一种用于向四层母板和主桥芯片基板提供稳定电源的布局结构。 在本发明中，在用于布局主桥芯片和功率环的底部焊料层的顶部信号层和功率路径上，去耦电容器连接在接地焊盘/焊球和电源接合焊盘/ 焊球的动力路径和动力环，从而为主桥芯片的运行提供稳定的电源。 在本发明中，与每个电源焊盘/焊球相连的接地焊盘/焊球可以是与功率焊盘/焊球最接近的接地焊盘/焊球。 此外，在主桥芯片基板的实施例中，去耦电容器可以设置在电源环的四个角落或者接合线下方，或者可以封装在模制化合物内部。

公开(公告)号：US6134701A

公开(公告)日：2000-10-17

申请号：US159441

申请日：1998-09-22

申请人： Shu-Hui Chen ,  Tsai-Sheng Chen ,  Nai-Shung Chang

发明人： Shu-Hui Chen ,  Tsai-Sheng Chen ,  Nai-Shung Chang

IPC分类号： G06F12/08 ,  H05K1/18 ,  G06F3/00

CPC分类号： H05K1/181 ,  G06F12/0893 ,  H05K2201/09227 ,  H05K2201/10689 ,  H05K2201/10734 ,  Y02P70/611

摘要： The present invention provides a computer motherboard having an Intel P54C compatible processor socket and a control chip having specifically arranged data pins and address pins which allows a short signal path arrangement from the processor socket to a cache tap RAM and a cache data RAM. The computer motherboard comprises a four-layer printed circuit board, a processor socket, a cache data RAM, a cache tag RAM, and a control chip. All these components are connected by using a high-order-bit data bus, a low-order-bit data bus, and an address bus through the top and bottom layers of the circuit board. The cache data RAM is positioned on the right side of the processor socket. The control chip is positioned on the top side of the cache data RAM and on the top-right side of the processor socket. It comprises an address section positioned at a bottom-middle portion of the control chip, a high-order-bit data section positioned at a bottom-right corner of the control chip, and a low-order-bit data section positioned at a bottom-left corner of the control chip. The cache tag RAM is positioned between the processor socket and the cache data RAM.

摘要翻译： 本发明提供了一种具有Intel P54C兼容处理器插座的计算机主板和具有特别布置的数据引脚和地址引脚的控制芯片，其允许从处理器插槽到高速缓存分接器RAM和高速缓存数据RAM的短信号路径布置。 计算机主板包括四层印刷电路板，处理器插座，高速缓存数据RAM，高速缓存标签RAM和控制芯片。 所有这些组件通过使用高位数据总线，低位数据总线和通过电路板的顶层和底层的地址总线连接。 缓存数据RAM位于处理器插槽的右侧。 控制芯片位于高速缓存数据RAM的顶侧，并位于处理器插槽的右上侧。 它包括位于控制芯片的底部中间部分的地址部分，位于控制芯片的右下角的高位数据部分和位于底部的低位数据部分 - 控制芯片的左角。 高速缓存标签RAM位于处理器插槽和高速缓存数据RAM之间。

公开(公告)号：US06888071B2

公开(公告)日：2005-05-03

申请号：US10710731

申请日：2004-07-30

申请人： Nai-Shung Chang ,  Tsai-Sheng Chen ,  Shu-Hui Chen

发明人： Nai-Shung Chang ,  Tsai-Sheng Chen ,  Shu-Hui Chen

IPC分类号： H05K1/00 ,  H05K1/18 ,  H05K1/03

CPC分类号： H05K1/0295 ,  H05K1/0298 ,  H05K1/18 ,  H05K2201/09345 ,  H05K2201/09954 ,  H05K2201/10522 ,  H05K2201/10704 ,  H05K2201/10734

摘要： A layout structure of a central processing unit (CPU) that supports two different package techniques, comprising a motherboard that comprises the layout structure and a layout method. The layout structure of the preferred embodiment according to the present invention from up to down sequentially places a top signal layer, a grounded layer, a power layer having a grounded potential, and a bottom solder layer in the area where the signals of the CPU are coupled to the signals of the control chip, so that the signals that are placed on the bottom solder layer can refer to a grounded potential area of the power layer. Therefore, part of signals of the CPU that are coupled to the control chip can be placed on the bottom solder layer. Since the preferred embodiment of the present invention provides more flexibility in the placement design, a layout structure that supports the Pentium IV CPUs of different package techniques can be designed on the motherboard of the 4 layers stack structure, and these two CPUs can be supported by the same control chip.

摘要翻译： 支持两种不同包装技术的中央处理单元（CPU）的布局结构，包括包括布局结构和布局方法的主板。 根据本发明的优选实施例的布局结构从上到下顺序地在CPU的信号区域中放置顶层信号层，接地层，具有接地电位的功率层和底部焊料层 耦合到控制芯片的信号，使得放置在底部焊料层上的信号可以指功率层的接地电位区域。 因此，耦合到控制芯片的CPU的部分信号可以放置在底部焊料层上。 由于本发明的优选实施例在布局设计中提供了更多的灵活性，因此可以在四层堆栈结构的主板上设计支持不同封装技术的Pentium IV CPU的布局结构，并且这两个CPU可以被 相同的控制芯片。

公开(公告)号：US06794744B2

公开(公告)日：2004-09-21

申请号：US10064426

申请日：2002-07-12

申请人： Nai-Shung Chang ,  Tsai-Sheng Chen ,  Shu-Hui Chen

发明人： Nai-Shung Chang ,  Tsai-Sheng Chen ,  Shu-Hui Chen

IPC分类号： H01L2352

CPC分类号： H05K1/0295 ,  H05K1/0298 ,  H05K1/18 ,  H05K2201/09345 ,  H05K2201/09954 ,  H05K2201/10522 ,  H05K2201/10704 ,  H05K2201/10734

摘要： A layout structure of a central processing unit (CPU) that supports two different package techniques, having a motherboard that comprising the layout structure and a layout method. The layout structure of the preferred embodiment according to the present invention from up to down sequentially placed a top signal layer, a grounded layer, a power layer having an operating potential area and a grounded potential area, and a bottom solder layer in the area where the signals of the CPU are coupled to the signals of the control chip, so that the signals that are placed on the bottom solder layer can refer to a grounded potential area of the power layer.

摘要翻译： 中央处理单元（CPU）的布局结构，其支持两种不同的封装技术，具有包括布局结构的主板和布局方法。 根据本发明的优选实施例的布局结构从上到下顺序地放置了顶部信号层，接地层，具有工作电位区域的功率层和接地电位区域，以及底部焊料层， CPU的信号耦合到控制芯片的信号，使得放置在底部焊料层上的信号可以指功率层的接地电位区域。

公开(公告)号：US06877102B2

公开(公告)日：2005-04-05

申请号：US10013983

申请日：2001-12-10

申请人： Nai-Shung Chang ,  Tsai-Sheng Chen ,  Shu-Hui Chen

发明人： Nai-Shung Chang ,  Tsai-Sheng Chen ,  Shu-Hui Chen

IPC分类号： G06F13/40 ,  G06F1/04

CPC分类号： G06F13/4068

摘要： A chipset to support multiple CPU's and a layout method thereof. Those independent signal lines for delivering high frequency clock signals of the chipset are isolated from using by other signals without being multiplexed. Trace length of the independent signal line is shorter than that of the others. The spaces between the independent signal line and others are also larger than that between other signal lines. Signal transmission quality is significantly upgraded because the high frequency clock signal is not multiplexed and isolated from others.

摘要翻译： 支持多CPU的芯片组及其布局方法。 用于传送芯片组的高频时钟信号的这些独立信号线与其他信号的使用隔离而不被复用。 独立信号线的跟踪长度短于其他信号线。 独立信号线与其他信号线之间的空间也大于其他信号线之间的间隔。 信号传输质量显着升高，因为高频时钟信号不被复用并与其隔离。

公开(公告)号：US06377510B2

公开(公告)日：2002-04-23

申请号：US09756586

申请日：2001-01-09

申请人： Nai-Shung Chang ,  Tsai-Sheng Chen ,  Shu-Hui Chen

发明人： Nai-Shung Chang ,  Tsai-Sheng Chen ,  Shu-Hui Chen

IPC分类号： G11C700

CPC分类号： G06F13/1694

摘要： A memory control system for controlling write-enable signals. The memory control system has a first memory slot having a write-enable pin thereon, a second memory slot having a first write-enable pin and a second write-enable pin thereon and a control chipset having a write-enable pin and a dual-purpose write-enable/memory-parity-data pin thereon. The write-enable pin of the control chipset is connected to the write-enable pin of the first memory slot and the first write-enable pin of the second memory slot. The write-enable/memory-parity-data pin of the control chipset is connected to the second write-enable pin of the second memory slot. In this invention, since the design of the write-enable system is more flexible, length of trace line on a computer board can be greatly reduced. In addition, the system permits the incorporation of one cycle (1T) timing into design of memory access commands.

摘要翻译： 一种用于控制写使能信号的存储器控​​制系统。 存储器控制系统具有在其上具有写使能引脚的第一存储器插槽，其上具有第一写使能引脚和第二写使能引脚的第二存储器插槽以及具有写使能引脚和双引脚引脚的控制芯片组， 目的写入/存储器奇偶校验数据引脚。 控制芯片组的写使能引脚连接到第一存储器插槽的写使能引脚和第二存储器插槽的第一写使能引脚。 控制芯片组的写使能/存储器奇偶校验数据引脚连接到第二存储器插槽的第二写使能引脚。 在本发明中，由于写使能系统的设计更灵活，所以可以大大减少计算机板上的迹线长度。 此外，该系统允许将一个周期（1T）定时并入到存储器访问命令的设计中。

公开(公告)号：US06844620B2

公开(公告)日：2005-01-18

申请号：US10183078

申请日：2002-06-26

申请人： Nai-Shung Chang ,  Shu-Hui Chen

发明人： Nai-Shung Chang ,  Shu-Hui Chen

IPC分类号： H01L23/34 ,  H01L23/48 ,  H01L23/498 ,  H01L23/50 ,  H01L23/52 ,  H01L29/00 ,  H01L31/00 ,  H05K1/11 ,  H05K1/18

CPC分类号： H01L23/49838 ,  H01L23/50 ,  H01L24/48 ,  H01L2224/05599 ,  H01L2224/45099 ,  H01L2224/48227 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19105 ,  H01L2924/30107 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2924/00012

摘要： The present invention is a placement that is utilized in a 4 layers motherboard and a main bridge chip substrate. The layout adds a placement of the power rings and the power paths on the top signal layer and the bottom solder layer of the main bridge chip on the motherboard, the second layer and the third layer are planned as grounded layers, so that all signals on the top signal layer and the bottom solder layer on the motherboard can easily refer to the grounded layer. The layout of the power ring and the power path on the top signal layer on the motherboard is symmetrical to the layout of the power ring and the power path on the bottom solder layer on the motherboard, and all power paths couple to the corresponding power rings. The power bonding pads/solder balls are arranged on the area where the power rings and the power paths pass through, and the moderate quantity of the grounded bonding pads are arranged on the both sides of the power paths. Regarding to the layout of the main bridge chip substrate, the power of the graphics module, memory, subaltern bridge and APG are placed on the third layer and the bottom layer of the main bridge chip substrate. Moreover, more vias are provided to couple to the power paths.

摘要翻译： 本发明是用于4层母板和主桥芯片基板的放置。 布局增加了主板上的主桥芯片的顶层信号层和底层焊料层上的功率环和功率路径的布置，第二层和第三层被计划为接地层，使得所有信号 主板上的顶层信号层和底层焊料层可以很容易地指接地层。 电源环的布局和主板顶层信号层上的电源路径对称于主板上电源环的布局和底层焊料层上的电源路径，所有的电源路径都耦合到相应的电源环 。 电源接合焊盘/焊球布置在电源环和电源路径通过的区域上，并且在电源路径的两侧布置适量的接地焊盘。 关于主桥芯片基板的布局，图形模块，存储器，次级桥和APG的功率被放置在主桥芯片基板的第三层和底层上。 此外，提供更多的通孔以耦合到电源路径。

公开(公告)号：US06384346B1

公开(公告)日：2002-05-07

申请号：US09688037

申请日：2000-10-12

申请人： Nai-Shung Chang ,  Ching-Fu Chuang ,  Hsiu-Wen Ho ,  Chia-Hsing Yuo ,  Shu-Hui Chen

发明人： Nai-Shung Chang ,  Ching-Fu Chuang ,  Hsiu-Wen Ho ,  Chia-Hsing Yuo ,  Shu-Hui Chen

IPC分类号： H01R909

CPC分类号： H05K7/1459 ,  H05K1/0216 ,  H05K2201/044 ,  H05K2201/09236

摘要： A trace layout of a printed circuit board (PCB) is provided with a north bridge, at least a peripheral component interconnect (PCI) slot, and an accelerate graphics port (AGP) slot. The PCB includes at least a first trace layer and a second trace layer under the first trace layer. The AGP slot is mounted between the north bridge and the PCI slot. The PCB further includes a number of first traces, and a number of second traces. The first traces are used for connecting the north bridge to the PCI slot while the second traces are used to connect the north bridge to the AGP slot. Some of the first traces are on the second trace layer under the AGP slot, while the other of the first traces are on the first trace layer or the second trace layer and trace aside the AGP slot. Most of the second traces are on the first trace layer and the other of the second traces are on the second trace layer.

摘要翻译： 印刷电路板（PCB）的迹线布局提供有北桥，至少外围组件互连（PCI）插槽和加速图形端口（AGP）插槽。 PCB包括至少第一迹线层和第一迹线层下的第二迹线层。 AGP插槽安装在北桥和PCI插槽之间。 PCB还包括多个第一迹线和多个第二迹线。 第一条迹线用于将北桥连接到PCI插槽，而第二条路径用于将北桥连接到AGP插槽。 一些第一个迹线位于AGP插槽下的第二个跟踪层上，而第一个迹线中的另一个迹线位于第一个跟踪层或第二个跟踪层上，并跟踪AGP插槽。 大多数第二迹线位于第一迹线层上，而第二迹线中的另一条迹线位于第二迹线层上。

公开(公告)号：US06459045B1

公开(公告)日：2002-10-01

申请号：US09924880

申请日：2001-08-08

申请人： Nai-Shung Chang ,  Shu-Hui Chen

发明人： Nai-Shung Chang ,  Shu-Hui Chen

IPC分类号： H05K103

CPC分类号： H05K1/141 ,  H05K1/0218 ,  H05K1/0263 ,  H05K3/368 ,  H05K2201/0715 ,  H05K2201/09309 ,  H05K2201/096

摘要： A circuit sub-board for regulating constant power source and strengthening ground connections. The circuit sub-board is a double-layered printed circuit board having a large surface power-source layer and a ground-connection layer. The circuit sub-board is utilized to cover the insufficiently ground-covered main board signaling lines as well as insufficiently ground-connected power and ground signaling lines on the main board. With the installation of the circuit sub-board, signals can be transmitted more reliably and with less interference.

摘要翻译： 用于调节恒定电源并加强接地连接的电路子板。 电路子板是具有大表面电源层和接地连接层的双层印刷电路板。 电路子板用于覆盖主板不足的主板信号线，以及主板上的接地电源和接地信号线不足。 随着电路子板的安装，信号可以更可靠地传输，干扰更小。