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公开(公告)号：US06098788A
公开(公告)日：2000-08-08
申请号：US926401
申请日：1997-09-09
CPC分类号： B29C33/38 , B29C33/302 , Y10T428/24322
摘要： A seamless micromechanical object is cast by forming a multilevel mold, filling the mold, and selectively removing the mold with respect to the micromechanical object. The mold can have a first level having a first opening therein, and a second level on the first level, the second level having a second opening therein, the second opening smaller than the first opening. The object may contain a controlled void, for example a micromechanical auger with a void formed therethrough to be used as a capillary to drain off fluids when the auger is in use.
摘要翻译： 通过形成多层模具，填充模具并相对于微机械物体选择性地移除模具来铸造无缝微机械物体。 模具可以具有在其中具有第一开口的第一层和第一层上的第二层，第二层在其中具有第二开口，第二开口小于第一开口。 该物体可以包含受控的空隙，例如具有穿过其形成的空隙的微机械螺旋钻，用作毛细管以在使用螺旋推运器时排出流体。
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公开(公告)号：US06199269B1
公开(公告)日：2001-03-13
申请号：US08956752
申请日：1997-10-23
IPC分类号： B23P1900
CPC分类号： G02B26/0841 , Y10T29/4979 , Y10T29/49799 , Y10T29/53
摘要： An aid to the manipulation of microfabricated micro tools in manufacturing and assembly is disclosed. A sequence of micro tools and a manipulator are connected to one another via attachment links as a combination. The attachment links are optimized to readily allow severing of individual micro tools from the combination as needed. The manipulator provides an aid for handling the combination via probe, pliers, clasping, mating or other device. This facilitates human or machine interaction with the combination of micro tools, either for subsequent processing, or for the assembly of the micro tools into a completed product.
摘要翻译： 公开了在制造和组装中对微加工微型工具的操纵的帮助。 一系列微型工具和操纵器通过连接作为一个组合相互连接。 附件链接被优化以容易地允许根据需要从组合中分离各个微型工具。 操纵器提供了通过探头，钳子，夹紧，配合或其他装置处理组合的辅助。 这有助于人类或机器与微型工具的组合相互作用，用于后续处理，或者将微型工具组装成完整的产品。
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公开(公告)号：US6031286A
公开(公告)日：2000-02-29
申请号：US808927
申请日：1997-02-28
IPC分类号： G02B6/12 , G02B6/13 , G02B6/132 , H01L23/473 , H01L23/34
CPC分类号： G02B6/131 , G02B6/132 , H01L23/473 , G02B2006/12176 , H01L2924/0002 , Y10S366/03
摘要： A semiconductor device or other suitable substrate and method with single or multi layers of buried micro pipes are disclosed. This is achieved by controlling the aspect ratio of trenches as well as controlling the deposition characteristics of the material used to fill the trenches. A buried micro pipe is formed by filling a trench that has a height which is larger than a width thereof, so that the trench filler material lines sidewalls and bottom of the trench, and covers the top of the trench to form the micro pipe within the trench. Another layer can be formed over the filler material and planarized. Alternatively, the filler material itself can be planarized. Forming trenches in the planarized layer, and repeating the above steps forms a second set of buried micro pipes in these new trenches. This forms a semiconductor device having multiple layer of buried micro pipes. Via holes may be etched to contact a micro pipe, or to inter connect micro pipes buried at different levels. Thus, instead of eliminating defective voids in trenches, the voids are controlled to form the micro pipes, which may be used to circulate a cooling fluid, or lined with a conductive material to form a micro light pipe channel, or buried conductive pipes.
摘要翻译： 公开了一种具有单层或多层埋入微管的半导体器件或其它合适的衬底和方法。 这通过控制沟槽的纵横比以及控制用于填充沟槽的材料的沉积特性来实现。 通过填充具有大于其宽度的高度的沟槽而形成埋入的微管，使得沟槽填充材料管道沟槽的侧壁和底部，并且覆盖沟槽的顶部以在该沟槽内部形成微管 沟。 可以在填料材料上形成另一层并进行平面化。 或者，填充材料本身可以被平坦化。 在平坦化层中形成沟槽，并重复上述步骤，在这些新的沟槽中形成第二组埋入的微管。 这形成具有多层埋藏微管的半导体器件。 可以蚀刻通孔以接触微管，或者将不同层次的微管相互连接。 因此，不是消除沟槽中的有缺陷的空隙，而是控制空隙以形成可用于循环冷却流体或用导电材料衬里以形成微光管通道的微管或埋入的导电管。
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公开(公告)号：US06228744B1
公开(公告)日：2001-05-08
申请号：US09427898
申请日：1999-10-27
IPC分类号： H01L2176
CPC分类号： G02B6/131 , G02B6/132 , G02B2006/12176 , H01L23/473 , H01L2924/0002 , Y10S366/03 , H01L2924/00
摘要： A semiconductor device or other suitable substrate and method with single or multi layers of buried micro pipes are disclosed. This is achieved by controlling the aspect ratio of trenches as well as controlling the deposition characteristics of the material used to fill the trenches. A buried micro pipe is formed by filling a trench that has a height which is larger than a width thereof, so that the trench filler material lines sidewalls and bottom of the trench, and covers the top of the trench to form the micro pipe within the trench. Another layer can be formed over the filler material and planarized. Alternatively, the filler material itself can be planarized. Forming trenches in the planarized layer, and repeating the above steps forms a second set of buried micro pipes in these new trenches. This forms a semiconductor device having multiple layer of buried micro pipes. Via holes may be etched to contact a micro pipe, or to inter connect micro pipes buried at different levels Thus, instead of eliminating defective voids in trenches, the voids are controlled to form the micro pipes, which may be used to circulate a cooling fluid, or lined with a conductive material to form a micro light pipe channel, or buried conductive pipes.
摘要翻译： 公开了一种具有单层或多层埋入微管的半导体器件或其它合适的衬底和方法。 这通过控制沟槽的纵横比以及控制用于填充沟槽的材料的沉积特性来实现。 通过填充具有大于其宽度的高度的沟槽而形成埋入的微管，使得沟槽填充材料管道沟槽的侧壁和底部，并且覆盖沟槽的顶部以在该沟槽的内部形成微管 沟。 可以在填料材料上形成另一层并进行平面化。 或者，填充材料本身可以被平坦化。 在平坦化层中形成沟槽，并重复上述步骤，在这些新的沟槽中形成第二组埋入的微管。 这形成具有多层埋藏微管的半导体器件。 可以蚀刻通孔以接触微管，或者将不同级别的微管相互连接。因此，不用消除沟槽中的有缺陷的空隙，可以控制空隙以形成微管，这可以用来循环冷却流体 或用导电材料衬里形成微光管通道，或埋入导电管。
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公开(公告)号：US5712702A
公开(公告)日：1998-01-27
申请号：US761169
申请日：1996-12-06
申请人： Vincent James McGahay , James Gardner Ryan , Michael Jay Shapiro , Christopher Joseph Waskiewicz
发明人： Vincent James McGahay , James Gardner Ryan , Michael Jay Shapiro , Christopher Joseph Waskiewicz
CPC分类号： C23C16/4405 , C23C16/52
摘要： A marker element is included in a deposition chamber. After use of the chamber to deposit films or coatings on workpieces, the chamber is cleaned to remove materials which may contaminate future processing of workpieces in the chamber. The composition of the gas exhausted from the chamber during the cleaning process is monitored, and a characteristic of the marker element is sensed. The cleaning gas is terminated in response to the sensed characteristic of the marker element having a predetermined value, such as a peak intensity or the return to a baseline value after peaking. The present invention effectively solves the problem of overcleaning or undercleaning the chamber based upon an estimated film thickness build up.
摘要翻译： 标记元件包括在沉积室中。 在使用室以在工件上沉积膜或涂层之后，清洁室以除去可能污染腔室中工件的未来加工的材料。 监测在清洁过程中从室中排出的气体的组成，并且检测标记元件的特性。 清洁气体响应于具有预定值（例如峰值强度）的标记元件的感测特性或峰值后的基线值的返回而终止。 本发明基于估计的膜厚度累积有效地解决了腔室过度清洁或欠清洁的问题。
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公开(公告)号：US5843363A
公开(公告)日：1998-12-01
申请号：US414241
申请日：1995-03-31
IPC分类号： H01L21/306 , B23K26/06 , B23K26/18 , B23K26/40 , H01L21/268 , H01L21/311 , H05K3/00 , B23K26/00 , B32B31/18
CPC分类号： B23K26/0661 , B23K26/18 , B23K26/40 , H01L21/311 , H01L21/31105 , B23K2201/40 , B23K2203/172 , B23K2203/50 , H05K3/0017
摘要： A process for ablation etching through one or more layers of dielectric materials while not etching an underlying conductive material layer comprises selecting parameters whereby the ablation process automatically stops when the conductive material layer is reached, or monitoring the process for end point detection of the desired degree of ablation. Parameters selected are the absorptivity of the dielectric layer versus that of the conductive material layer. End point detection includes monitoring radiant energy reflected from the workpiece or the content of the materials being ablated from the workpiece.
摘要翻译： 在不蚀刻下面的导电材料层的情况下，通过一个或多个介电材料层进行烧蚀蚀刻的方法包括选择参数，由此当达到导电材料层时，消融过程自动停止，或者监测所需程度的终点检测过程 的消融。 选择的参数是电介质层与导电材料层的吸收率。 终点检测包括监测从工件反射的辐射能或从工件烧蚀的材料的内容物。
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7.发明授权Method for selective material deposition on one side of raised or recessed features 失效在凸起或凹陷特征的一侧上选择性材料沉积的方法
公开(公告)号：US5885425A
公开(公告)日：1999-03-23
申请号：US470604
申请日：1995-06-06
IPC分类号： C23C14/34 , B81C3/00 , C23C14/04 , C23C14/22 , H01L21/203 , H01L21/285
CPC分类号： C23C14/225 , C23C14/046 , H01J37/3447
摘要： An apparatus and method provide deposition on a surface by angled sputtering using a collimation grid having angled vanes which limit the distribution of trajectories of particles in at least one coordinate direction around a central axis oriented at an angle of less than 90.degree. to said surface; resulting in improved uniformity of deposition and/or selective favoring of deposition on surfaces at a high angle to the deposition surface (e.g. sidewalls). Substantially parallel orientation and uniform spacing of the sputtering target and deposition surface provides good uniformity of results over the deposition surface. The angled trajectories of sputtered particles provides improved deposition on sides of upstanding mandrel features and filling of recessed features of high aspect ratio, especially when the collimation grid is rotated about an axis generally perpendicular to the deposition surface. Angled, collimated deposition also allows for control of deposition at potentially sub-lithographic feature sizes by using portions of features as a mask with deposition being performed only on remaining exposed portions of features or deposition on selected sides of a mandrel feature. Sidewall image transfer techniques may thus be extended to non-symmetrical and singular features. At very shallow angles to the deposition surface, deposited material has a fibrous texture with greatly increased effective surface area.
摘要翻译： 一种装置和方法通过使用具有成角度的叶片的准直栅格通过成角度的溅射来提供沉积在表面上，所述准直网格限制了颗粒在至少一个坐标方向上的轨迹的分布，所述中心轴线围绕所述表面以小于90°的角度定向; 导致沉积的均匀性和/或选择性地有利于在沉积表面（例如侧壁）上以高角度沉积在表面上。 溅射靶和沉积表面的基本平行取向和均匀间隔提供了超过沉积表面的结果的良好均匀性。 溅射颗粒的倾斜轨迹提供了直立心轴特征的侧面上的改进的沉积以及高纵横比的凹陷特征的填充，特别是当准直格栅围绕大致垂直于沉积表面的轴线旋转时。 倾斜的准直沉积还允许通过使用特征部分作为掩模来控制潜在的亚光刻特征尺寸下的沉积，仅在特征的剩余暴露部分或沉积在心轴特征的选定侧上进行沉积。 因此，侧壁图像传送技术可以扩展到非对称和奇异的特征。 与沉积表面非常浅的角度，沉积材料具有大大增加的有效表面积的纤维织构。
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8.发明授权ESD structure that employs a schottky-barrier to reduce the likelihood of latch-up 失效使用肖特基势垒的ESD结构减少闭锁的可能性
公开(公告)号：US5763918A
公开(公告)日：1998-06-09
申请号：US740134
申请日：1996-10-22
IPC分类号： H01L27/04 , H01L21/822 , H01L27/02 , H01L27/092 , H01L29/47 , H01L29/872 , H01L23/62
CPC分类号： H01L27/0255 , H01L2924/0002
摘要： The preferred embodiment of the present invention overcomes the limitations of the prior art and provides a device and method to decrease the latch-up susceptibility of an ESD structure by suppressing the injection of minority carriers that cause transistor action to occur. This is accomplished, for example, by using a metal contact to the n-substrate or n-well in place of or in parallel with the prior art p-diffusion. Using such a metal contact forms a Schottky Barrier Diode (SBD) with the ESD structure. Since the SBD is a majority-carrier device, negligible minority carriers are injected when the SBD is in forward bias, thereby reducing the likelihood of latch-up.
摘要翻译： 本发明的优选实施例克服了现有技术的局限，并且提供了一种通过抑制引起晶体管作用发生的少数载流子的注入来减小ESD结构的闭锁敏感性的装置和方法。 这是通过例如通过使用与n衬底或n阱的金属接触来代替或与现有技术的p-扩散并行来实现的。 使用这种金属接触形成具有ESD结构的肖特基势垒二极管（SBD）。 由于SBD是多数载波器件，当SBD处于正向偏置时，可以忽略少数载流子，从而降低闩锁的可能性。
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公开(公告)号：US5757879A
公开(公告)日：1998-05-26
申请号：US707808
申请日：1996-08-30
CPC分类号： G21K1/10
摘要： An damascene x-ray mask comprises an oxide membrane layer having trenches formed therein defining an x-ray mask pattern. The trenches are filled with collimated, sputtered tungsten sputtered in a relatively high pressure environment. The result is a dense, low stress tungsten film completely filling the trenches. Damascene refers to the process by which the mask is formed. The mask is formed on a silicon substrate and then the substrate is etched away from the bottom side leaving substantially just the oxide layer and the collimated tungsten. The oxide layer is transparent to x-rays and the collimated tungsten layer is opaque to x-rays.
摘要翻译： 镶嵌式x射线掩模包括其中形成有沟槽的氧化物膜层，其限定了x射线掩模图案。 在相对较高的压力环境中溅射的准直溅射钨的沟槽中充满了沟槽。 结果是致密的低应力钨膜完全填充沟槽。 大马士革是指形成掩模的过程。 掩模形成在硅衬底上，然后衬底从底侧蚀刻掉，基本上仅留下氧化物层和准直钨。 氧化物层对x射线透明，准直钨层对X射线不透明。
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10.发明授权Process for depositing a conductive thin film upon an integrated circuit substrate 失效在集成电路基板上沉积导电薄膜的工艺
公开(公告)号：US5711858A
公开(公告)日：1998-01-27
申请号：US496999
申请日：1995-06-30
IPC分类号： C23C14/04 , C23C14/18 , C23C14/34 , H01L21/768 , H01L23/532
CPC分类号： H01L23/53219 , C23C14/046 , C23C14/185 , C23C14/34 , H01L21/76877 , H01L2924/0002
摘要： An improved process for depositing a conductive thin film upon an integrated circuit substrate by collimated sputtering is disclosed. The sputtered films are alloys of aluminum; a preferred alloying metal is magnesium. The sputtered films of the invention have a more uniform orientation of grains than sputtered aluminum copper silicon alloy films. Such processes are especially useful in the fabrication of integrated circuit devices having aluminum alloy wiring elements.
摘要翻译： 公开了一种通过准直溅射在集成电路基板上沉积导电薄膜的改进方法。 溅射膜是铝合金; 优选的合金金属是镁。 本发明的溅射膜具有比溅射的铝铜硅合金膜更均匀的晶粒取向。 这种方法在具有铝合金布线元件的集成电路器件的制造中特别有用。
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