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公开(公告)号：US5757879A
公开(公告)日：1998-05-26
申请号：US707808
申请日：1996-08-30
CPC分类号： G21K1/10
摘要： An damascene x-ray mask comprises an oxide membrane layer having trenches formed therein defining an x-ray mask pattern. The trenches are filled with collimated, sputtered tungsten sputtered in a relatively high pressure environment. The result is a dense, low stress tungsten film completely filling the trenches. Damascene refers to the process by which the mask is formed. The mask is formed on a silicon substrate and then the substrate is etched away from the bottom side leaving substantially just the oxide layer and the collimated tungsten. The oxide layer is transparent to x-rays and the collimated tungsten layer is opaque to x-rays.
摘要翻译： 镶嵌式x射线掩模包括其中形成有沟槽的氧化物膜层，其限定了x射线掩模图案。 在相对较高的压力环境中溅射的准直溅射钨的沟槽中充满了沟槽。 结果是致密的低应力钨膜完全填充沟槽。 大马士革是指形成掩模的过程。 掩模形成在硅衬底上，然后衬底从底侧蚀刻掉，基本上仅留下氧化物层和准直钨。 氧化物层对x射线透明，准直钨层对X射线不透明。
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公开(公告)号：US06444565B1
公开(公告)日：2002-09-03
申请号：US09896204
申请日：2001-06-29
IPC分类号： H01L214761
CPC分类号： H01L23/5226 , H01L21/7682 , H01L21/76885 , H01L21/76897 , H01L23/53223 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： A structure and process to define a via/interconnect structure is described. The structure is formed by reactive ion etching (RIE) where vias are formed first then the interconnects. The disclosed method relies on first depositing a metal with a thickness equivalent to the total height of the via and interconnect. Once vias are delineated by forming a hard mask and lithography, the lines are patterned using a lithographic step. Vias and lines are formed using lithography and RIE in one step and interfacial integrity is maintained resulting in high electromigration performance.
摘要翻译： 描述了定义通孔/互连结构的结构和过程。 该结构由反应离子蚀刻（RIE）形成，其中首先形成通孔和互连。 所公开的方法依赖于首先沉积具有等于通孔和互连的总高度的厚度的金属。 一旦通过形成硬掩模和光刻来描绘通孔，则使用光刻步骤对线进行图案化。 通过光刻和RIE在一个步骤中形成通孔和线，并保持界面完整性，导致高的电迁移性能。
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公开(公告)号：US5920486A
公开(公告)日：1999-07-06
申请号：US699095
申请日：1996-08-16
IPC分类号： G06F17/50 , H01L27/02 , H01L27/092 , G06F17/00
CPC分类号： G06F17/5068 , H01L27/0207 , H01L27/092
摘要： The invention provides a technique, given a netlist containing a description of the terminal connections and the length and width of each device in a circuit, for automatically producing a layout for each device in that circuit.
摘要翻译： 本发明提供了一种技术，给出了一种网表，其包含终端连接的描述以及电路中每个设备的长度和宽度，用于自动地产生该电路中的每个设备的布局。
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4.发明授权High aspect ratio low resistivity lines/vias with a tungsten-germanium alloy hard cap 失效高长宽比低电阻率线/通孔与钨 - 锗合金硬帽
公开(公告)号：US5731245A
公开(公告)日：1998-03-24
申请号：US738901
申请日：1996-10-28
IPC分类号： H01L21/28 , H01L21/203 , H01L21/205 , H01L21/3205 , H01L21/321 , H01L21/768 , H01L23/52 , H01L23/522 , H01L23/532 , H01L21/302
CPC分类号： H01L21/76849 , H01L21/321 , H01L21/3212 , H01L21/76807 , H01L21/76838 , H01L21/76867 , H01L21/76877 , H01L21/76886 , H01L23/5226 , H01L23/53209 , H01L23/53219 , H01L23/53242 , H01L23/53247 , H01L2924/0002 , H01L2924/09701 , Y10T428/12486 , Y10T428/12528 , Y10T428/12674 , Y10T428/12736 , Y10T428/1284 , Y10T428/12889 , Y10T428/12896
摘要： A structure and method for fabricating circuits which use field effect transistors (FETs), bipolar transistors, or BiCMOS (combined Bipolar/Complementary Metal Oxide Silicon structures), uses low temperature germanium gas flow to affect metals and alloys deposited in high aspect ratio structures including lines and vias. By using a germanium gas flow, germanium (Ge) will be introduced in a surface reaction which prevents voids and side seams and which also provides a passivating layer of CuGe. If a hard cap is needed for surface passivation or a wear-resistance application, the GeH.sub.4 gas followed by WF.sub.6 can be used to produce an in-situ hard cap and polish stop of W.sub.x Ge.sub.y, a tungsten-germanium alloy. Further, high aspect ratio vias/lines (aspect ratio of 3 or more) can be filled by utilizing low pressures and high temperatures (i.e., below 450.degree. C.) without degrading the underlying metals.
摘要翻译： 使用场效应晶体管（FET），双极晶体管或BiCMOS（组合双极/互补金属氧化物硅结构）的电路的制造结构和方法使用低温锗气流来影响以高纵横比结构沉积的金属和合金，包括 线和通孔。 通过使用锗气流，将在表面反应中引入锗（Ge），其防止空隙和侧面接缝，并且还提供CuGe的钝化层。 如果表面钝化或耐磨应用需要硬帽，则可以使用WF6之后的GeH4气体来生产钨 - 锗合金WxGey的原位硬盖和抛光停止。 此外，可以通过利用低压和高温（即低于450℃）来填充高纵横比通孔/线（纵横比为3以上），而不降低底层金属。
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公开(公告)号：US08682634B2
公开(公告)日：2014-03-25
申请号：US13613061
申请日：2012-09-13
申请人： Saeed Bagheri , Fook-Luen Heng , Rajiv Vasant Joshi , Kafai Lai , David Osmond Melville , Saibal Mukhopadhyay , Alan E Rosenbluth , Rama N. Singh , Kehan Tian
发明人： Saeed Bagheri , Fook-Luen Heng , Rajiv Vasant Joshi , Kafai Lai , David Osmond Melville , Saibal Mukhopadhyay , Alan E Rosenbluth , Rama N. Singh , Kehan Tian
CPC分类号： G06F17/5009 , G03F1/36 , G03F1/70 , G06F2217/10
摘要： Techniques are presented that include accessing results of forward simulations of circuit yield, the results including at least circuit yield results including simulated device shapes. Using the circuit yield results, high-level traits of at least the simulated device shapes are determined. Based on the determined high-level traits and using the circuit yield results, a compact model for predicted yield is constructed, the compact model including a plurality of adjustable parameters, and the constructing the compact model for predicted yield including adjusting the adjustable parameters until at least one first predetermined criterion is met. An optimization problem is constructed including at least the compact model for yield, an objective, and a plurality of constraints. Using the optimization problem, the objective is modified subject to the plurality of constraints until at least one second predetermined criterion is met.
摘要翻译： 提出了包括访问电路产量正向模拟的结果的技术，结果至少包括电路产量结果，包括模拟设备形状。 使用电路产量结果，确定至少模拟装置形状的高级特征。 基于确定的高水平特征和使用电路产量结果，构建了一种预测产量的紧凑模型，该紧凑模型包括多个可调参数，并构建了用于预测产量的紧凑模型，包括调整可调参数直到 满足至少一个第一预定标准。 构建最优化问题，其至少包括用于产量，目标和多个约束的紧凑模型。 使用优化问题，根据多个约束修改目标，直到满足至少一个第二预定标准。
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公开(公告)号：US06943105B2
公开(公告)日：2005-09-13
申请号：US10782808
申请日：2004-02-23
申请人： Rajiv Vasant Joshi
发明人： Rajiv Vasant Joshi
IPC分类号： H01L21/768 , H01L21/4763
CPC分类号： H01L21/76877 , H01L21/76838 , H01L21/7684
摘要： A soft metal conductor for use in a semiconductor device which has an uppermost layer consisting of grains having grain sizes sufficiently large so as to provide a substantially scratch-free surface upon polishing in a subsequent polishing step. The invention also provides a method for making a soft metal conductor that has a substantially scratch-free surface upon polishing by a multi-step deposition process, i.e., first sputtering at a higher temperature and then sputtering at a lower temperature and followed by another high temperature sputtering process. The invention further discloses a method for forming a substantially scratch-free surface on a soft metal conductor by first depositing a soft metal layer at a low deposition temperature and then annealing the soft metal layer at a higher temperature to increase the grain size of the metal. The invention also discloses a dual-step deposition method for making a soft metal conductor for use in an electronic device by first depositing a first layer of metal by a physical vapor deposition technique to a first thickness, and then depositing a second layer of metal on top of the first layer of metal to a second thickness larger than the first thickness by a method of chemical vapor deposition, electroplating or electroless plating. The first deposition process may further be conducted by a chemical vapor deposition technique, with the second deposition process conducted by a physical vapor deposition technique.
摘要翻译： 一种用于半导体器件的软金属导体，其具有由具有足够大的晶粒尺寸的晶粒组成的最上层，以便在随后的抛光步骤中在抛光时提供基本无划痕的表面。 本发明还提供一种用于制造软金属导体的方法，该软金属导体在通过多步沉积工艺进行研磨时具有基本上无划痕的表面，即，在较高温度下的第一次溅射，然后在较低温度下溅射，然后再进一步高 温度溅射工艺。 本发明还公开了一种在软金属导体上形成基本无划痕的表面的方法，首先在低沉积温度下沉积软金属层，然后在较高温度下退火软金属层以增加金属的晶粒尺寸 。 本发明还公开了一种双步沉积方法，用于通过首先通过物理气相沉积技术将第一金属层沉积到第一厚度上，然后将第二层金属沉积在第一层上，形成用于电子器件的软金属导体 通过化学气相沉积，电镀或化学镀的方法将第一层金属的顶部设置成大于第一厚度的第二厚度。 第一沉积工艺可以进一步通过化学气相沉积技术进行，第二沉积工艺通过物理气相沉积技术进行。
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公开(公告)号：US06335569B1
公开(公告)日：2002-01-01
申请号：US09112885
申请日：1998-07-09
申请人： Rajiv Vasant Joshi
发明人： Rajiv Vasant Joshi
IPC分类号： H01L2348
CPC分类号： H01L21/76805 , H01L21/7684 , H01L21/76877 , H01L23/5226 , H01L23/53223 , H01L2924/0002 , H01L2924/00
摘要： A soft metal conductor for use in a semiconductor device which has an uppermost layer consisting of grains having grain sizes sufficiently large so as to provide a substantially scratch-free surface upon polishing in a subsequent polishing step. The invention also provides a method for making a soft metal conductor that has a substantially scratch-free surface upon polishing by a multi-step deposition process, i.e., first sputtering at a higher temperature and then sputtering at a lower temperature and followed by another high temperature sputtering process. The invention further discloses a method for forming a substantially scratch-free surface on a soft metal conductor by first depositing a soft metal layer at a low deposition temperature and then annealing the soft metal layer at a higher temperature to increase the grain size of the metal. The invention also discloses a dual-step deposition method for making a soft metal conductor for use in an electronic device by first depositing a first layer of metal by a physical vapor deposition technique to a first thickness, and then depositing a second layer of metal on top of the first layer of metal to a second thickness larger than the first thickness by a method of chemical vapor deposition, electroplating or electroless plating. The first deposition process may further be conducted by a chemical vapor deposition technique, with the second deposition process conducted by a physical vapor deposition technique.
摘要翻译： 一种用于半导体器件的软金属导体，其具有由具有足够大的晶粒尺寸的晶粒组成的最上层，以便在随后的抛光步骤中在抛光时提供基本无划痕的表面。 本发明还提供一种用于制造软金属导体的方法，该软金属导体在通过多步沉积工艺进行研磨时具有基本上无划痕的表面，即，在较高温度下的第一次溅射，然后在较低温度下溅射，然后再进一步高 温度溅射工艺。 本发明还公开了一种在软金属导体上形成基本无划痕的表面的方法，首先在低沉积温度下沉积软金属层，然后在较高温度下退火软金属层以增加金属的晶粒尺寸 。 本发明还公开了一种双步沉积方法，用于通过首先通过物理气相沉积技术将第一金属层沉积到第一厚度上，然后将第二层金属沉积在第一层上，形成用于电子器件的软金属导体 通过化学气相沉积，电镀或化学镀的方法将第一层金属的顶部设置成大于第一厚度的第二厚度。 第一沉积工艺可以进一步通过化学气相沉积技术进行，第二沉积工艺通过物理气相沉积技术进行。
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公开(公告)号：US5901304A
公开(公告)日：1999-05-04
申请号：US816600
申请日：1997-03-13
申请人： Wei Hwang , Rajiv Vasant Joshi , Yasunao Katayama
发明人： Wei Hwang , Rajiv Vasant Joshi , Yasunao Katayama
CPC分类号： G06F13/1689 , G11C7/1072 , G11C7/22 , G11C8/12 , Y02B60/1228
摘要： A quasi-synchronous DRAM circuit uses a plurality of asynchronous DRAM macros organized in memory banks. An interface conversion circuit receives external synchronous control signals and generates internal control signals for each of the plurality of asynchronous DRAM macros. A data buffer circuit is connected to each of the asynchronous DRAM macros by in internal input/output (I/O) bus. The interface conversion circuit controls the data buffer to provide synchronous burst of data through frequency conversion.
摘要翻译： 准同步DRAM电路使用组织在存储体中的多个异步DRAM宏。 接口转换电路接收外部同步控制信号，并为多个异步DRAM宏中的每一个生成内部控制信号。 数据缓冲电路通过内部输入/输出（I / O）总线连接到每个异步DRAM宏。 接口转换电路控制数据缓冲器，通过频率转换提供数据同步脉冲串。
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公开(公告)号：US20130185046A1
公开(公告)日：2013-07-18
申请号：US13613061
申请日：2012-09-13
申请人： Saeed Bagheri , Fook-Luen Heng , Rajiv Vasant Joshi , Kafai Lai , David Osmond Melville , Saibal Mukhopadhyay , Alan E. Rosenbluth , Rama N. Singh , Kehan Tian
发明人： Saeed Bagheri , Fook-Luen Heng , Rajiv Vasant Joshi , Kafai Lai , David Osmond Melville , Saibal Mukhopadhyay , Alan E. Rosenbluth , Rama N. Singh , Kehan Tian
IPC分类号： G06F17/50
CPC分类号： G06F17/5009 , G03F1/36 , G03F1/70 , G06F2217/10
摘要： Techniques are presented that include accessing results of forward simulations of circuit yield, the results including at least circuit yield results including simulated device shapes. Using the circuit yield results, high-level traits of at least the simulated device shapes are determined. Based on the determined high-level traits and using the circuit yield results, a compact model for predicted yield is constructed, the compact model including a plurality of adjustable parameters, and the constructing the compact model for predicted yield including adjusting the adjustable parameters until at least one first predetermined criterion is met. An optimization problem is constructed including at least the compact model for yield, an objective, and a plurality of constraints. Using the optimization problem, the objective is modified subject to the plurality of constraints until at least one second predetermined criterion is met.
摘要翻译： 提出了包括访问电路产量正向模拟的结果的技术，结果至少包括电路产量结果，包括模拟设备形状。 使用电路产量结果，确定至少模拟装置形状的高级特征。 基于确定的高水平特征和使用电路产量结果，构建了一种预测产量的紧凑模型，该紧凑模型包括多个可调参数，并构建了用于预测产量的紧凑模型，包括调整可调参数直到 满足至少一个第一预定标准。 构建最优化问题，其至少包括用于产量，目标和多个约束的紧凑模型。 使用优化问题，根据多个约束修改目标，直到满足至少一个第二预定标准。
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公开(公告)号：US20100327958A1
公开(公告)日：2010-12-30
申请号：US12494460
申请日：2009-06-30
CPC分类号： H03K17/0822
摘要： A dormant mode target semiconductor device within a leakage current target unit is identified for mitigating leakage current to prevent it from reaching catastrophic runaway. A leakage current shift monitor unit is electrically connected to the output node of the leakage current target unit and collects leakage current from the selected target semiconductor device for two consecutive predefined temporal periods and measures the difference between the collected leakage currents. A comparator receives and compares the outputs of the current shift monitor unit and a reference voltage generator. The comparator propagates an alert signal to the leakage current target unit when the leakage voltage output from the leakage current shift monitor unit exceeds the reference voltage, a condition that indicates that the leakage current is about to approach catastrophic runaway levels. This alert signal switches the target semiconductor device to an active mode for leakage mitigation, which includes a repair voltage from a repair voltage generator applied to the gate of the target semiconductor device.
摘要翻译： 识别泄漏电流目标单元内的休眠模式目标半导体器件，以减轻漏电流，防止其达到灾难性的失控。 泄漏电流移动监视器单元电连接到泄漏电流目标单元的输出节点，并在两个连续的预定义时间周期内从所选择的目标半导体器件收集泄漏电流，并测量所收集的漏电流之间的差异。 比较器接收并比较当前移位监视器单元和参考电压发生器的输出。 当从泄漏电流移动监视器单元输出的泄漏电压超过参考电压时，比较器将报警信号传播到泄漏电流目标单元，表示泄漏电流即将接近灾难性失控水平的条件。 该警报信号将目标半导体器件切换到用于泄漏减轻的活动模式，其包括施加到目标半导体器件的栅极的修复电压发生器的修复电压。
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