公开(公告)号：US20060248248A1

公开(公告)日：2006-11-02

申请号：US11475916

申请日：2006-06-28

申请人： Naoki Mitsuishi

发明人： Naoki Mitsuishi

IPC分类号： G06F13/00

CPC分类号： G06F13/405 ,  G06F13/362

摘要： It is aimed at improving the efficiency of data transfer processing and the concurrent data processing on a central processing unit. A data transfer device can independently request a bus access right and output an address to a first bus (IBUS) and a second bus (PBUS). It is possible to solve the state of competing for the bus access right between both buses. While the bus access right of one bus is granted for reading or writing, the bus access right of the other bus can be released. When the data transfer device releases the bus access right for the first bus, a central processing unit can process data. In response to one data transfer start request, the bus access right is requested for one bus and the other bus, There is not used a sequence of requesting the bus access right in response to different data transfer requests for respective buses. It is possible to simplify a handshake sequence of a data transfer request and its acknowledgment.

摘要翻译： 它旨在提高数据传输处理的效率和中央处理单元的并发数据处理。 数据传输设备可以独立地请求总线访问权限，并将地址输出到第一总线（IBUS）和第二总线（PBUS）。 可以解决两条公交车之间的公共汽车通行权竞争的状态。 当一条总线的总线访问权限被授予读取或写入时，可以释放另一条总线的总线访问权限。 当数据传输装置释放第一总线的总线访问权时，中央处理单元可以处理数据。 响应于一个数据传输启动请求，对于一个总线和另一个总线请求总线访问权限。响应于各个总线的不同数据传输请求，没有使用请求总线访问权限的顺序。 可以简化数据传输请求的握手顺序及其确认。

公开(公告)号：US20060156075A1

公开(公告)日：2006-07-13

申请号：US11299971

申请日：2005-12-13

申请人： Naoki Mitsuishi

发明人： Naoki Mitsuishi

IPC分类号： G06F11/00

CPC分类号： G06F11/0793 ,  G06F11/0721 ,  G06F11/0757

摘要： Error recovery processing is performed to minimize the influence of malfunction when an error is detected. When an error occurs in a normal program execution state, control branches to a predetermined error handling routine shown by exceptional handling vectors or the like. While executing the instruction that writes zero to a timer counter in an interval not extending an overflow cycle, the error handling routine of a CPU performs processing for inhibiting a fatal operation in accordance with a control target system. An example of inhibiting a fatal operation is to deactivate output signals of a microcomputer. Upon completion of the error handling, the monitoring timer is stopped, and the processing of the CPU is changed to the normal reset processing routine.

摘要翻译： 执行错误恢复处理以在检测到错误时最小化故障的影响。 当正常程序执行状态发生错误时，控制分支到由异常处理向量等所示的预定错误处理程序。 在执行在不延长溢出周期的间隔内将零写入定时器计数器的指令时，CPU的错误处理程序根据控制目标系统执行用于禁止致命操作的处理。 抑制致命操作的示例是停用微计算机的输出信号。 完成错误处理后，监视定时器停止，CPU的处理更改为正常的复位处理程序。

公开(公告)号：US20050210221A1

公开(公告)日：2005-09-22

申请号：US11130200

申请日：2005-05-17

申请人： Naoki Mitsuishi

发明人： Naoki Mitsuishi

IPC分类号： G06F3/00 ,  G06F11/30 ,  G06F13/14 ,  G06F13/16 ,  G06F13/28 ,  G06F15/00

CPC分类号： G06F13/16 ,  G06F13/28

摘要： A microcomputer is provided with a data-transfer unit such as a DMA (direct memory access) controller for controlling a transfer of data through an external bus. Used in an access to an external device controlled by the data-transfer unit, a bus-interface means of the microcomputer includes a buffer-register means which can be specified as either a source location or a destination location of a data transfer. Thus, an internal-bus master such as a CPU employed in the microcomputer is capable of reading out information such as a packet command from the buffer-register means at a high speed through an internal bus without using the external bus and, hence, capable of carrying out an operation reflecting a transfer control condition specified by the packet command.

公开(公告)号：US20080201564A1

公开(公告)日：2008-08-21

申请号：US12105188

申请日：2008-04-17

申请人： Naoki Mitsuishi ,  Shinichi Shibahara ,  Takahiro Okubo

发明人： Naoki Mitsuishi ,  Shinichi Shibahara ,  Takahiro Okubo

IPC分类号： G06F9/30

CPC分类号： G06F9/3802 ,  G06F9/30032 ,  G06F9/30036 ,  G06F9/30145 ,  G06F9/30149 ,  G06F9/30167 ,  G06F9/3814 ,  G06F9/3842

摘要： An object of the present invention is to achieve fast data processing. A unit (FF) is included for selecting whether a central processing unit (CPU) performs instruction reading in units of 16 bits (a first word length) or in units of 32 bits (a second word length). Depending on whether instruction reading is performed in units of 16 bits or 32 bits, increment values (+2 and +4) by which a program counter (PC) is incremented are switched. Data reading or writing is performed in units of a given data length irrespective of the selecting unit. When the CPU issues a request for instruction reading in units of 16 bits or 32 bits or for data reading or writing, a bus control unit performs reading or writing a predetermined number of times according to a bus width designated for a resource located at an address specified in the request. The bus control unit causes the CPU to wait until an instruction of 16 or 32 bits long (read data) requested by the CPU gets ready.

摘要翻译： 本发明的目的是实现快速的数据处理。 包括单元（FF），用于选择中央处理单元（CPU）以16位（第一字长）为单位或以32位（第二字长）为单位执行指令读取。 取决于指令读取是以16位还是32位为单位执行，程序计数器（PC）递增的增量值（+2和+4）被切换。 无论选择单位如何，以给定数据长度为单位进行数据读取或写入。 当CPU以16位或32位为单位发出指令读取请求或进行数据读取或写入时，总线控制单元根据位于地址的资源指定的总线宽度执行预定次数的读取或写入 在请求中指定。 总线控制单元使CPU等待，直到CPU请求的16位或32位长（读取数据）的指令准备就绪。

公开(公告)号：US20080034150A1

公开(公告)日：2008-02-07

申请号：US11879499

申请日：2007-07-18

申请人： Naoki Mitsuishi

发明人： Naoki Mitsuishi

IPC分类号： G06F12/00

CPC分类号： G06F21/62 ,  G06F21/78 ,  G06F2221/2105 ,  G06F2221/2143 ,  G11C8/20

摘要： The present invention realizes improvement in security in the case where a nonvolatile memory device which can be read/written by random access is mounted as a memory for storing both of a program and data. In a microcomputer including: a CPU enabling a computing process based on a preset program; and a nonvolatile memory device which can be read/written by random access of the CPU, the nonvolatile memory device includes, in a part of its memory area, an area in which nonvolatile holding is invalid. By using the area as an area for storing secret data to be held, the secret data to be held is prevented from being nonvolatile-held in the nonvolatile memory device. Thus, improvement in security is achieved.

摘要翻译： 通过安装可以通过随机存取读取/写入的非易失性存储装置作为存储程序和数据两者的存储器，本发明实现了安全性的提高。 一种微型计算机，包括：CPU，其能够基于预设程序进行计算处理; 以及可以通过CPU的随机存取读取/写入的非易失性存储器件，非易失性存储器件在其存储区域的一部分中包括非易失性保持无效的区域。 通过使用该区域作为用于存储要保存的秘密数据的区域，防止将要保持的秘密数据非易失性地保持在非易失性存储装置中。 因此，实现了安全性的提高。

公开(公告)号：US5736948A

公开(公告)日：1998-04-07

申请号：US592974

申请日：1996-01-29

申请人： Naoki Mitsuishi ,  Hiroyuki Kobayashi ,  Hiroshi Saito ,  Mitsumasa Satoh

发明人： Naoki Mitsuishi ,  Hiroyuki Kobayashi ,  Hiroshi Saito ,  Mitsumasa Satoh

IPC分类号： G06F3/05 ,  G06F15/78 ,  H03K17/693 ,  H03M1/12 ,  H03M1/14 ,  H03M1/18 ,  H03M1/36 ,  H03M1/00

CPC分类号： H03M1/1215 ,  H03K17/693 ,  H03M1/1225 ,  H03M1/145 ,  H03M1/46

摘要： In a semiconductor integrated circuit device having an A/D converter incorporated therein, a plurality of input channels are provided and input analog signals supplied therefrom are respectively held by a plurality of sample-to-hold circuits. The analog signals are simultaneously sampled by using such a pipeline operation that a first sampling is performed so that an analog signal held by the first sampling is A/D-converted and a second sampling is performed so that an analog signal held by the second sampling is A/D-converted, and the plurality of sample-to-hold circuits.

摘要翻译： 在其中并入有A / D转换器的半导体集成电路器件中，提供多个输入通道，并且由其提供的输入模拟信号分别由多个采样保持电路保持。 通过使用进行第一次采样的这样的流水线操作来同时采样模拟信号，使得由第一采样保持的模拟信号被A / D转换并执行第二采样，使得由第二采样保持的模拟信号 被A / D转换，以及多个采样保持电路。

公开(公告)号：US5381556A

公开(公告)日：1995-01-10

申请号：US48410

申请日：1993-04-15

申请人： Naoki Mitsuishi ,  Atsushi Hirose

发明人： Naoki Mitsuishi ,  Atsushi Hirose

IPC分类号： G06F11/22 ,  G06F9/24 ,  G06F15/78 ,  G11C16/02 ,  G11C16/10 ,  G11C17/00

CPC分类号： G11C16/102 ,  G06F9/24

摘要： A semiconductor device is provided for implementing a single-chip microcomputer or the like, which micro-computer is compatible with a plurality of programmable ROM writing schemes. The device enhances the functionality and system flexibility of the single-chip microcomputer or the like while reducing development period and design and evaluation steps of a system incorporating the above-mentioned microcomputer. The single-chip microcomputer incorporates a programmable ROM (PROM), having a PROM mode for writing the programmable ROM by using a general-purpose ROM writer. The unit is provided with a write control signal for selectively specifying a writing scheme in the PROM mode to selectively switch between numbers and/or combinations of address signal and/or activation control signals to be supplied to the programmable ROM.

摘要翻译： 提供了一种用于实现单片机等的半导体器件，该微型计算机与多个可编程ROM写入方案兼容。 该装置在减少包含上述微型计算机的系统的开发周期和设计和评估步骤的同时增强了单片微机等的功能和系统灵活性。 单片机包含可编程ROM（PROM），其具有通过使用通用ROM写入器来写可编程ROM的PROM模式。 该单元具有写入控制信号，用于在PROM模式中选择性地指定写入方案，以选择性地切换要提供给可编程ROM的地址信号和/或激活控制信号的数字和/或组合。

公开(公告)号：US5084843A

公开(公告)日：1992-01-28

申请号：US513569

申请日：1990-04-24

申请人： Naoki Mitsuishi ,  Kiyoshi Matsubara ,  Yoh Takamori ,  Yoshiyuki Ozawa

发明人： Naoki Mitsuishi ,  Kiyoshi Matsubara ,  Yoh Takamori ,  Yoshiyuki Ozawa

IPC分类号： G06F12/14 ,  G11C16/06 ,  G11C16/16 ,  G11C16/22 ,  G11C16/26

CPC分类号： G11C16/16 ,  G06F12/1433 ,  G11C16/06 ,  G11C16/22 ,  G11C16/26

摘要： A volatile storage circuit for latching data is disposed outside a non-volatile memory array. Before a bulk erase of the memory array, some of the data items contained therein are transferred to and held by the storage circuit. The data items thus saved are rewritten to the non-volatile memory array after the bulk erase, or alternatively, on the basis of control data items transferred to the storage circuit, only regions designated by these data items are subjected to the bulk erase. Thus, in case of a bulk erase of an EEPROM, some of the stored data items can be preserved, so as to prevent illicit use of and maintain the integrity of the preserved data. Also the testing time of the data rewritten to the memory array is reduced because of the elimination of the need to test the memory area containing the preserved data in that only the integrity of the memory area containing data sourced externally need be tested.

公开(公告)号：US20060248254A1

公开(公告)日：2006-11-02

申请号：US11475937

申请日：2006-06-28

申请人： Naoki Mitsuishi

发明人： Naoki Mitsuishi

IPC分类号： G06F13/36

CPC分类号： G06F13/405 ,  G06F13/362

摘要： It is aimed at improving the efficiency of data transfer processing and the concurrent data processing on a central processing unit. A data transfer device can independently request a bus access right and output an address to a first bus (IBUS) and a second bus (PBUS). It is possible to solve the state of competing for the bus access right between both buses. While the bus access right of one bus is granted for reading or writing, the bus access right of the other bus can be released. When the data transfer device releases the bus access right for the first bus, a central processing unit can process data. In response to one data transfer start request, the bus access right is requested for one bus and the other bus, There is not used a sequence of requesting the bus access right in response to different data transfer requests for respective buses. It is possible to simplify a handshake sequence of a data transfer request and its acknowledgment.

公开(公告)号：US20050251615A1

公开(公告)日：2005-11-10

申请号：US11180554

申请日：2005-07-14

申请人： Naoki Mitsuishi

发明人： Naoki Mitsuishi

IPC分类号： G11C17/00 ,  G06F12/00 ,  G06F12/02 ,  G06F15/78 ,  G06F21/00 ,  G11C16/02

CPC分类号： G06F12/0223 ,  G06F15/7814 ,  G06F21/79

摘要： A single chip type microcomputer includes at least a central processing unit (CPU), a random-access memory (RAM), a mask read-only memory (CPU) and an electrically writable ROM such as an electrically erasable and programmable read-only memory (EEPROM). The electrically writable ROM stores both the user program and data to be preserved. The microcomputer includes further a memory for storing a write control program for controlling the write operation to the writable ROM, and the electrically writable ROM and the memory are disposed at mutually different address positions on the address space of CPU. The proportion of size of the user program region and the data region in the writable ROM can be selected in a free proportion.

摘要翻译： 单片式微型计算机至少包括中央处理单元（CPU），随机存取存储器（RAM），掩模只读存储器（CPU）和电可写ROM，诸如电可擦除和可编程只读存储器 （EEPROM）。 电可写ROM存储要保存的用户程序和数据。 微型计算机还包括用于存储用于控制对可写ROM的写入操作的写入控制程序的存储器，并且电可写ROM和存储器设置在CPU的地址空间上的相互不同的地址位置处。 用户程序区域和可写入ROM中的数据区域的大小的比例可以自由选择。