公开(公告)号：US07253465B2

公开(公告)日：2007-08-07

申请号：US10817004

申请日：2004-04-05

申请人： Naoki Yamamoto ,  Yoshitaka Tadaki ,  Hiroshige Kogayu

发明人： Naoki Yamamoto ,  Yoshitaka Tadaki ,  Hiroshige Kogayu

IPC分类号： H01L29/76

CPC分类号： H01L27/11526 ,  H01L21/28044 ,  H01L21/823842 ,  H01L27/1052 ,  H01L27/10814 ,  H01L27/10852 ,  H01L27/10873 ,  H01L27/10894 ,  H01L27/10897 ,  H01L27/11521 ,  H01L27/11534 ,  H01L27/11546 ,  H01L27/12 ,  H01L27/1203 ,  H01L28/84 ,  H01L28/91 ,  H01L29/4941

摘要： In a dual polymetal gate electrode, the contact resistance at the interface of silicon films increases due to mutual-diffusion of impurities of p-type and n-type silicon films through a refractory metal and metal nitride deposited thereon. A way of inhibiting the phenomenon is carbon implantation into a refractory metal and refractory metal nitride on the boundary of p-type silicon and n-type silicon, cutting the path, or isolating it by an insulator. Thereby, mutual-diffusion of impurities through a refractory metallic film and nitride film of refractory metal is inhibited, resulting in an increase in the contact resistance of metal nitride film and silicon film and a decrease in the deviation of threshold voltage of the MISFET.

摘要翻译： 在双重多金属栅电极中，由于p型和n型硅膜的杂质通过其上沉积的难熔金属和金属氮化物的相互扩散，硅膜界面处的接触电阻增加。 抑制现象的一种方法是将碳注入到p型硅和n型硅的边界上的难熔金属和难熔金属氮化物中，切割路径，或通过绝缘体隔离。 因此，杂质通过难熔金属膜和难熔金属的氮化物膜的相互扩散被抑制，导致金属氮化物膜和硅膜的接触电阻增加以及MISFET的阈值电压的偏差的降低。

公开(公告)号：US07375013B2

公开(公告)日：2008-05-20

申请号：US11396000

申请日：2006-04-03

申请人： Naoki Yamamoto ,  Yoshikazu Tanabe ,  Hiroshige Kogayu ,  Takehiko Yoshida

发明人： Naoki Yamamoto ,  Yoshikazu Tanabe ,  Hiroshige Kogayu ,  Takehiko Yoshida

IPC分类号： H01L21/28 ,  H01L21/44

CPC分类号： H01L29/4941 ,  H01L21/28044 ,  H01L21/28061 ,  H01L21/28176 ,  H01L21/28211 ,  H01L21/28556 ,  H01L21/324 ,  H01L27/10814 ,  H01L27/10873 ,  H01L27/10894

摘要： Formation of an WNX film 24 constituting a barrier layer of a gate electrode 7A having a polymetal structure is effected in an atmosphere containing a high concentration nitrogen gas, whereby release of N (nitrogen) from the WNX film 24 is suppressed in the heat treatment step after the formation of the gate electrode 7A.

摘要翻译： 在含有高浓度氮气的气氛中，形成构成具有多金属结构的栅电极7A的势垒层的WN X X膜24，从而从WN中释放N（氮） 在形成栅电极7A之后的热处理步骤中抑制了薄膜24。

公开(公告)号：US20060175651A1

公开(公告)日：2006-08-10

申请号：US11396000

申请日：2006-04-03

申请人： Naoki Yamamoto ,  Yoshikazu Tanabe ,  Hiroshige Kogayu ,  Takehiko Yoshida

发明人： Naoki Yamamoto ,  Yoshikazu Tanabe ,  Hiroshige Kogayu ,  Takehiko Yoshida

IPC分类号： H01L27/108 ,  H01L29/76 ,  H01L29/94 ,  H01L29/00

CPC分类号： H01L29/4941 ,  H01L21/28044 ,  H01L21/28061 ,  H01L21/28176 ,  H01L21/28211 ,  H01L21/28556 ,  H01L21/324 ,  H01L27/10814 ,  H01L27/10873 ,  H01L27/10894

摘要： Formation of an WNX film 24 constituting a barrier layer of a gate electrode 7A having a polymetal structure is effected in an atmosphere containing a high concentration nitrogen gas, whereby release of N (nitrogen) from the WNX film 24 is suppressed in the heat treatment step after the formation of the gate electrode 7A.

摘要翻译： 在含有高浓度氮气的气氛中，形成构成具有多金属结构的栅电极7A的势垒层的WN X X膜24，从而从WN中释放N（氮） 在形成栅电极7A之后的热处理步骤中抑制了薄膜24。

公开(公告)号：US07632744B2

公开(公告)日：2009-12-15

申请号：US12102306

申请日：2008-04-14

申请人： Naoki Yamamoto ,  Yoshikazu Tanabe ,  Hiroshige Kogayu ,  Takehiko Yoshida

发明人： Naoki Yamamoto ,  Yoshikazu Tanabe ,  Hiroshige Kogayu ,  Takehiko Yoshida

IPC分类号： H01L21/28 ,  H01L21/44

CPC分类号： H01L29/4941 ,  H01L21/28044 ,  H01L21/28061 ,  H01L21/28176 ,  H01L21/28211 ,  H01L21/28556 ,  H01L21/324 ,  H01L27/10814 ,  H01L27/10873 ,  H01L27/10894

摘要： Formation of an WNx film 24 constituting a barrier layer of a gate electrode 7A having a polymetal structure is effected in an atmosphere containing a high concentration nitrogen gas, whereby release of N (nitrogen) from the WNx film 24 is suppressed in the heat treatment step after the formation of the gate electrode 7A.

摘要翻译： 构成具有多金属结构的栅电极7A的阻挡层的WNx膜24的形成在含有高浓度氮气的气氛中进行，从而在热处理工序中抑制N（氮）从WNx膜24的释放 在形成栅电极7A之后。

公开(公告)号：US20080227251A1

公开(公告)日：2008-09-18

申请号：US12102306

申请日：2008-04-14

申请人： Naoki Yamamoto ,  Yoshikazu Tanabe ,  Hiroshige Kogayu ,  Takehiko Yoshida

发明人： Naoki Yamamoto ,  Yoshikazu Tanabe ,  Hiroshige Kogayu ,  Takehiko Yoshida

IPC分类号： H01L27/108

CPC分类号： H01L29/4941 ,  H01L21/28044 ,  H01L21/28061 ,  H01L21/28176 ,  H01L21/28211 ,  H01L21/28556 ,  H01L21/324 ,  H01L27/10814 ,  H01L27/10873 ,  H01L27/10894

摘要： Formation of an WNx film 24 constituting a barrier layer of a gate electrode 7A having a polymetal structure is effected in an atmosphere containing a high concentration nitrogen gas, whereby release of N (nitrogen) from the WNx film 24 is suppressed in the heat treatment step after the formation of the gate electrode 7A.

摘要翻译： 在含有高浓度氮气的气氛中，形成构成具有多金属结构的栅电极7A的势垒层的WN 膜24，从而从WN中释放出N（氮） 在形成栅电极7A之后，在热处理步骤中抑制了薄膜24。

公开(公告)号：US07053459B2

公开(公告)日：2006-05-30

申请号：US10468462

申请日：2001-10-31

申请人： Naoki Yamamoto ,  Yoshikazu Tanabe ,  Hiroshige Kogayu ,  Takehiko Yoshida

发明人： Naoki Yamamoto ,  Yoshikazu Tanabe ,  Hiroshige Kogayu ,  Takehiko Yoshida

IPC分类号： H01L29/00

CPC分类号： H01L29/4941 ,  H01L21/28044 ,  H01L21/28061 ,  H01L21/28176 ,  H01L21/28211 ,  H01L21/28556 ,  H01L21/324 ,  H01L27/10814 ,  H01L27/10873 ,  H01L27/10894

摘要： Formation of an WNx film 24 constituting a barrier layer of a gate electrode 7A having a polymetal structure is effected in an atmosphere containing a high concentration nitrogen gas, whereby release of N (nitrogen) from the WNx film 24 is suppressed in the heat treatment step after the formation of the gate electrode 7A.

摘要翻译： 在含有高浓度氮气的气氛中，形成构成具有多金属结构的栅电极7A的势垒层的WN 膜24，从而从WN中释放出N（氮） 在形成栅电极7A之后，在热处理步骤中抑制了薄膜24。

公开(公告)号：US20060245266A1

公开(公告)日：2006-11-02

申请号：US11409963

申请日：2006-04-25

申请人： Ryusuke Sahara ,  Mitsugu Kusunoki ,  Kazutaka Mori ,  Hiroshige Kogayu

发明人： Ryusuke Sahara ,  Mitsugu Kusunoki ,  Kazutaka Mori ,  Hiroshige Kogayu

IPC分类号： G11C7/10

CPC分类号： H03M1/1061 ,  H03M1/687 ,  H03M1/785 ,  H03M1/808

摘要： A DAC having a memory mat including a plurality of first memory cells, and a plurality of output lines connected to the plurality of first memory cells. Each of the plurality of memory cells has a first memory portion including bipolar transistors and storing information in non-volatility based on whether a junction of the bipolar transistors is destroyed or not, and a second memory portion connected to the first memory portion and for outputting information to corresponding one of the plurality of output lines. The DAC has a first mode in which information is transferred from the first memory portions to the second memory portions when the information is written into the second memory portions, and a second mode in which the second memory portions are specified externally and information is written into the second memory portions. Thus, the performance of a D/A converter can be improved.

摘要翻译： 具有包括多个第一存储单元的存储器垫的DAC和连接到多个第一存储单元的多个输出线。 多个存储单元中的每一个具有包括双极晶体管的第一存储器部分，并且基于双极晶体管的结是否被破坏来存储非易失性的信息，以及连接到第一存储器部分并用于输出的第二存储器部分 信息到多个输出行中的相应一个。 DAC具有第一模式，其中当信息被写入第二存储器部分时，信息从第一存储器部分传送到第二存储器部分，以及第二模式，其中第二存储器部分被外部指定并且信息被写入 第二存储器部分。 因此，可以提高D / A转换器的性能。

公开(公告)号：US20060244103A1

公开(公告)日：2006-11-02

申请号：US11411096

申请日：2006-04-26

申请人： Koji Ishikawa ,  Kazutaka Mori ,  Hiroshige Kogayu ,  Tamotsu Miyake ,  Mitsugu Kusunoki

发明人： Koji Ishikawa ,  Kazutaka Mori ,  Hiroshige Kogayu ,  Tamotsu Miyake ,  Mitsugu Kusunoki

IPC分类号： H01L27/082

CPC分类号： H01L23/5252 ,  H01L27/0823 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor apparatus includes a first transistor having a first emitter electrode, a first base electrode, and a first collector electrode in a region over a first region. Base lead-out polysilicon connecting the first base electrode and a first base region passes over a second region provided out of the first region and a resistor element is added. A writing voltage is reduced in an antifuse using two bipolar transistors.

公开(公告)号：US20080055140A1

公开(公告)日：2008-03-06

申请号：US11877561

申请日：2007-10-23

申请人： Ryusuke SAHARA ,  Mitsugu Kusunoki ,  Kazutaka Mori ,  Hiroshige Kogayu

发明人： Ryusuke SAHARA ,  Mitsugu Kusunoki ,  Kazutaka Mori ,  Hiroshige Kogayu

IPC分类号： H03M1/66

CPC分类号： H03M1/1061 ,  H03M1/687 ,  H03M1/785 ,  H03M1/808

摘要： A DAC having a memory mat including a plurality of first memory cells, and a plurality of output lines connected to the plurality of first memory cells. Each of the plurality of memory cells has a first memory portion including bipolar transistors and storing information in non-volatility based on whether a junction of the bipolar transistors is destroyed or not, and a second memory portion connected to the first memory portion and for outputting information to corresponding one of the plurality of output lines. The DAC has a first mode in which information is transferred from the first memory portions to the second memory portions when the information is written into the second memory portions, and a second mode in which the second memory portions are specified externally and information is written into the second memory portions. Thus, the performance of a D/A converter can be improved.

摘要翻译： 具有包括多个第一存储单元的存储器垫的DAC和连接到多个第一存储单元的多个输出线。 多个存储单元中的每一个具有包括双极晶体管的第一存储器部分，并且基于双极晶体管的结是否被破坏来存储非易失性的信息，以及连接到第一存储器部分并用于输出的第二存储器部分 信息到多个输出行中的相应一个。 DAC具有第一模式，其中当信息被写入第二存储器部分时，信息从第一存储器部分传送到第二存储器部分，以及第二模式，其中第二存储器部分被外部指定并且信息被写入 第二存储器部分。 因此，可以提高D / A转换器的性能。

公开(公告)号：US07310266B2

公开(公告)日：2007-12-18

申请号：US11409963

申请日：2006-04-25

申请人： Ryusuke Sahara ,  Mitsugu Kusunoki ,  Kazutaka Mori ,  Hiroshige Kogayu

发明人： Ryusuke Sahara ,  Mitsugu Kusunoki ,  Kazutaka Mori ,  Hiroshige Kogayu

IPC分类号： G11C11/40 ,  H03M1/66

CPC分类号： H03M1/1061 ,  H03M1/687 ,  H03M1/785 ,  H03M1/808

摘要： A DAC having a memory mat including a plurality of first memory cells, and a plurality of output lines connected to the plurality of first memory cells. Each of the plurality of memory cells has a first memory portion including bipolar transistors and storing information in non-volatility based on whether a junction of the bipolar transistors is destroyed or not, and a second memory portion connected to the first memory portion and for outputting information to corresponding one of the plurality of output lines. The DAC has a first mode in which information is transferred from the first memory portions to the second memory portions when the information is written into the second memory portions, and a second mode in which the second memory portions are specified externally and information is written into the second memory portions.

摘要翻译： 具有包括多个第一存储单元的存储器垫的DAC和连接到多个第一存储单元的多个输出线。 多个存储单元中的每一个具有包括双极晶体管的第一存储器部分，并且基于双极晶体管的结点是否被破坏来存储非易失性的信息，以及连接到第一存储器部分并用于输出的第二存储器部分 信息到多个输出行中的相应一个。 DAC具有第一模式，其中当信息被写入第二存储器部分时，信息从第一存储器部分传送到第二存储器部分，以及第二模式，其中第二存储器部分被外部指定并且信息被写入 第二存储器部分。