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    Fabrication process of a semiconductor integrated circuit device
    6.
    发明授权
    Fabrication process of a semiconductor integrated circuit device 有权
    半导体集成电路器件的制造工艺

    公开(公告)号：US06987069B2

    公开(公告)日：2006-01-17

    申请号：US10821842

    申请日：2004-04-12

    申请人： Yoshikazu Tanabe ,  Isamu Asano ,  Makoto Yoshida ,  Naoki Yamamoto ,  Masayoshi Saito ,  Nobuyoshi Natsuaki

    发明人： Yoshikazu Tanabe ,  Isamu Asano ,  Makoto Yoshida ,  Naoki Yamamoto ,  Masayoshi Saito ,  Nobuyoshi Natsuaki

    IPC分类号： H01L21/31

    CPC分类号： H01L21/28247 ,  H01L21/28061 ,  H01L21/28176 ,  H01L21/32105 ,  H01L21/823437 ,  H01L21/823468 ,  H01L21/823828 ,  H01L21/823857 ,  H01L27/1052 ,  H01L27/10873 ,  H01L27/10894 ,  H01L29/4941

    摘要： With a view to preventing the oxidation of a metal film at the time of light oxidation treatment after gate patterning and at the same time to making it possible to control the reproducibility of oxide film formation and homogeneity of oxide film thickness at gate side-wall end portions, in a gate processing step using a poly-metal, a gate electrode is formed by patterning a gate electrode material which has been deposited over a semiconductor wafer 1A having a gate oxide film formed thereon and has a poly-metal structure and then, the principal surface of the semiconductor wafer 1A heated to a predetermined temperature or vicinity thereof is supplied with a hydrogen gas which contains water at a low concentration, the water having been formed from hydrogen and oxygen by a catalytic action, to selectively oxidize the principal surface of the semiconductor wafer 1A, whereby the profile of the side-wall end portions of the gate electrode is improved.

    摘要翻译： 为了防止栅极图案化后的光氧化处理时的金属膜的氧化，同时能够控制氧化膜形成的再现性和栅侧壁端的氧化膜厚度的均匀性 在使用多金属的栅极处理步骤中，通过对已在其上形成有栅极氧化膜的半导体晶片1A上淀积的具有多金属结构的栅电极材料进行构图来形成栅电极， 向被加热到预定温度或附近的半导体晶片1A的主表面供给含有低浓度的水的氢气，由氢和氧通过催化作用形成的水，以选择性地氧化 半导体晶片1A的主表面，从而提高了栅电极的侧壁端部的轮廓。

    Semiconductor integrated circuit device and method for manufacturing the same
    8.
    发明授权
    Semiconductor integrated circuit device and method for manufacturing the same 有权
    半导体集成电路器件及其制造方法

    公开(公告)号：US06936550B2

    公开(公告)日：2005-08-30

    申请号：US10760358

    申请日：2004-01-21

    申请人： Naoki Yamamoto ,  Yoshikazu Tanabe

    发明人： Naoki Yamamoto ,  Yoshikazu Tanabe

    IPC分类号： H01L29/78 ,  H01L21/28 ,  H01L21/316 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/423 ,  H01L29/43 ,  H01L29/49 ,  H01L29/51 ,  H01L21/44

    CPC分类号： H01L21/28194 ,  H01L21/28079 ,  H01L21/28176 ,  H01L21/28185 ,  H01L21/28202 ,  H01L21/823828 ,  H01L21/823857 ,  H01L29/517 ,  H01L29/518

    摘要： A manufacturing method for a semiconductor integrated circuit device comprises forming, over a gate insulating film which has been formed over the main surface of a single crystal silicon substrate to have an effective film thickness less than 5 nm in terms of SiO2, a W film as a gate electrode material, and heat treating the silicon substrate in a water-vapor- and hydrogen-containing gas atmosphere having a water vapor/hydrogen partial pressure ratio set at a ratio permitting oxidation of silicon without substantial oxidation of the W film, whereby defects of the gate insulating film right under the W film are repaired. In this way, in a MISFET having a metal gate electrode formed over a ultra-thin gate insulating film having an effective film thickness less than 5 nm in terms of SiO2, defects of the gate insulating film can be repaired without oxidizing the metal gate electrode.

    摘要翻译： 一种半导体集成电路器件的制造方法，包括在形成于单晶硅衬底的主表面上的栅极绝缘膜上形成有效膜厚度以SiO 2换算为5nm以下， 作为栅极电极材料的W膜，并且在水蒸气和氢气气氛中对硅衬底进行热处理，其中水蒸气/氢分压比设定为允许氧化硅的比例， W膜的氧化，从而修复W膜正下方的栅极绝缘膜的缺陷。 以这种方式，在具有金属栅电极的MISFET中，栅极绝缘膜的缺陷可以在SiO 2上具有有效膜厚小于5nm的超薄栅绝缘膜 在不氧化金属栅电极的情况下进行修复。

    Semiconductor integrated circuit device and method for manufacturing the same
    9.
    发明授权
    Semiconductor integrated circuit device and method for manufacturing the same 有权
    半导体集成电路器件及其制造方法

    公开(公告)号：US06737341B1

    公开(公告)日：2004-05-18

    申请号：US09577671

    申请日：2000-05-25

    申请人： Naoki Yamamoto ,  Yoshikazu Tanabe

    发明人： Naoki Yamamoto ,  Yoshikazu Tanabe

    IPC分类号： H01L213205

    CPC分类号： H01L21/28194 ,  H01L21/28079 ,  H01L21/28176 ,  H01L21/28185 ,  H01L21/28202 ,  H01L21/823828 ,  H01L21/823857 ,  H01L29/517 ,  H01L29/518

    摘要： A manufacturing method for a semiconductor intergraded circuit device comprises forming, over a gate insulating film which has been formed over a gate insulating film which has been formed over the main surface of a single crystal silicon substrate to have an effective film thinkness less than 5 nm in terms of SiO2, a W film as a gate electrode material, and heat treating the silicon substrate in a water-vapor- and hydrogen-containing gas atmosphere having a water vapor/hydrogen partial pressure ratio set at a ratio permitting oxidation of silicon without substantial oxidation of the W film, whereby defects of the gate insulating film right under the W film are repaired. In this way, in a MISFET having a metal gate electrode formed over a ultra-thin gate insulating film having an effective film thinkness less than 5 nm in term of SiO2, defectes of the gate insulating film can be repaired without oxidizing the metal gate electrode.

    摘要翻译： 一种半导体集成电路器件的制造方法，包括在形成在单晶硅衬底的主表面上的栅极绝缘膜上形成的栅极绝缘膜上形成有效膜思想小于5nm 在SiO 2方面，将W膜作为栅电极材料，并将硅衬底在含有允许氧化硅的比例设定的水蒸气/氢气分压比的水蒸汽和氢气气氛中进行热处理而没有 W膜的大量氧化，从而修复W膜正下方的栅极绝缘膜的缺陷。 以这种方式，在具有金属栅电极的MISFET中，在SiO 2以上有效膜思想小于5nm的超薄栅极绝缘膜上形成，可以在不使金属栅电极氧化的情况下修复栅极绝缘膜的缺陷 。