公开(公告)号：US06696849B2

公开(公告)日：2004-02-24

申请号：US09964708

申请日：2001-09-28

申请人： Naoto Ban ,  Masaaki Namba ,  Akio Hasebe ,  Yuji Wada ,  Ryuji Kohno ,  Akira Seito ,  Yasuhiro Motoyama

发明人： Naoto Ban ,  Masaaki Namba ,  Akio Hasebe ,  Yuji Wada ,  Ryuji Kohno ,  Akira Seito ,  Yasuhiro Motoyama

IPC分类号： G01R3102

CPC分类号： G01R31/2831

摘要： A testing apparatus and a fabricating method of a semiconductor integrated circuit device for reducing the fabrication cost by placing, in the wafer level burn-in, divided contactors in equally contact with the full surface of wafer, enabling repair of each contactor and improving the yield of contactors. The cassette structure of the mechanical pressurizing system in the testing apparatus is structured with a plurality of divided silicon contactor blocks and a guide frame for integrating these blocks and employs the wafer full surface simultaneous contact system of the divided contactor integration type. Each probe of the silicon contactor is equally placed in contact in the predetermined pressure with each test pad of each chip of the test wafer by mechanically pressuring each silicon contactor block which moves individually, the test control signal is supplied to each chip and this test result signal is obtained for the wafer level burn-in test.

摘要翻译： 一种半导体集成电路器件的测试装置和制造方法，用于通过在晶片级老化中放置与晶片的整个表面均匀接触的分割的接触器来降低制造成本，从而能够修复每个接触器并提高产量 的接触器。 测试装置中的机械加压系统的盒式结构由多个分开的硅接触器块和用于集成这些块的引导框架构成，并且采用分开的接触器一体化型的晶片全表面同时接触系统。 硅接触器的每个探针通过机械加压每个单独移动的硅接触器块，将测试控制信号提供给每个芯片，并且测试结果与测试晶片的每个芯片的每个测试焊盘等同地以预定压力接触 获得晶片级老化测试信号。

公开(公告)号：US06455335B1

公开(公告)日：2002-09-24

申请号：US09653624

申请日：2000-08-31

申请人： Ryuji Kohno ,  Tetsuo Kumazawa ,  Makoto Kitano ,  Akihiko Ariga ,  Yuji Wada ,  Naoto Ban ,  Shuji Shibuya ,  Yasuhiro Motoyama ,  Kunio Matsumoto ,  Susumu Kasukabe ,  Terutaka Mori ,  Hidetaka Shigi ,  Takayoshi Watanabe

发明人： Ryuji Kohno ,  Tetsuo Kumazawa ,  Makoto Kitano ,  Akihiko Ariga ,  Yuji Wada ,  Naoto Ban ,  Shuji Shibuya ,  Yasuhiro Motoyama ,  Kunio Matsumoto ,  Susumu Kasukabe ,  Terutaka Mori ,  Hidetaka Shigi ,  Takayoshi Watanabe

IPC分类号： G01R3126

CPC分类号： G01R3/00 ,  G01R1/0735

摘要： Dispersion of load may be kept within an allowance even when a plurality of probes in a large area are pressed in batch by pressing the probes provided in a membrane to a wafer by applying a pressure load to a plurality of places of a plane of pressure members on the side opposite from the wafer in a probe test step/burn-in test step which is one of semiconductor device manufacturing steps. It is then possible to provide semiconductor devices and a manufacturing method thereof which enhance the reliability and productivity of the semiconductor devices by probing a large number of integrated circuits or a large size integrated circuit in the same time.

公开(公告)号：US07198962B2

公开(公告)日：2007-04-03

申请号：US10411283

申请日：2003-04-11

申请人： Ryuji Kohno ,  Tetsuo Kumazawa ,  Makoto Kitano ,  Akihiko Ariga ,  Yuji Wada ,  Naoto Ban ,  Shuji Shibuya ,  Yasuhiro Motoyama ,  Kunio Matsumoto ,  Susumu Kasukabe ,  Terutaka Mori ,  Hidetaka Shigi ,  Takayoshi Watanabe

发明人： Ryuji Kohno ,  Tetsuo Kumazawa ,  Makoto Kitano ,  Akihiko Ariga ,  Yuji Wada ,  Naoto Ban ,  Shuji Shibuya ,  Yasuhiro Motoyama ,  Kunio Matsumoto ,  Susumu Kasukabe ,  Terutaka Mori ,  Hidetaka Shigi ,  Takayoshi Watanabe

IPC分类号： G01R31/26 ,  H01L21/66 ,  H01L21/00 ,  H01L21/48

CPC分类号： G01R3/00 ,  G01R1/0735

摘要： Dispersion of load may be kept within an allowance even when a plurality of probes in a large area are pressed in batch by pressing the probes provided in a membrane to a wafer by applying a pressure load to a plurality of places of a plane of pressure members on the side opposite from the wafer in a probe test step/burn-in test step which is one of semiconductor device manufacturing steps. It is then possible to provide semiconductor devices and a manufacturing method thereof which enhance the reliability and productivity of the semiconductor devices by probing a large number of integrated circuits or a large size integrated circuit in the same time.

摘要翻译： 即使当大量区域中的多个探针通过将设置在膜中的探针压迫到晶片而将压力负载施加到压力构件的平面的多个位置时，负载的分散也可以保持在容许范围内 在作为半导体器件制造步骤之一的探针测试步骤/老化测试步骤中与晶片相对的一侧。 因此，可以提供通过同时探测大量集成电路或大尺寸集成电路来提高半导体器件的可靠性和生产率的半导体器件及其制造方法。

公开(公告)号：US06566150B2

公开(公告)日：2003-05-20

申请号：US10171695

申请日：2002-06-17

申请人： Ryuji Kohno ,  Tetsuo Kumazawa ,  Makoto Kitano ,  Akihiko Ariga ,  Yuji Wada ,  Naoto Ban ,  Shuji Shibuya ,  Yasuhiro Motoyama ,  Kunio Matsumoto ,  Susumu Kasukabe ,  Terutaka Mori ,  Hidetaka Shigi ,  Takayoshi Watanabe

发明人： Ryuji Kohno ,  Tetsuo Kumazawa ,  Makoto Kitano ,  Akihiko Ariga ,  Yuji Wada ,  Naoto Ban ,  Shuji Shibuya ,  Yasuhiro Motoyama ,  Kunio Matsumoto ,  Susumu Kasukabe ,  Terutaka Mori ,  Hidetaka Shigi ,  Takayoshi Watanabe

IPC分类号： G01R3126

CPC分类号： G01R3/00 ,  G01R1/0735

摘要： Dispersion of load may be kept within an allowance even when a plurality of probes in a large area are pressed in batch by pressing the probes provided in a membrane to a wafer by applying a pressure load to a plurality of places of a plane of pressure members on the side opposite from the wafer in a probe test step/burn-in test step which is one of semiconductor device manufacturing steps. It is then possible to provide semiconductor devices and a manufacturing method thereof which enhance the reliability and productivity of the semiconductor devices by probing a large number of integrated circuits or a large size integrated circuit in the same time.

公开(公告)号：US06197603B1

公开(公告)日：2001-03-06

申请号：US09157153

申请日：1998-09-18

申请人： Ryuji Kohno ,  Tetsuo Kumazawa ,  Makoto Kitano ,  Akihiko Ariga ,  Yuji Wada ,  Naoto Ban ,  Shuji Shibuya ,  Yasuhiro Motoyama ,  Kunio Matsumoto ,  Susumu Kasukabe ,  Terutaka Mori ,  Hidetaka Shigi ,  Takayoshi Watanabe

发明人： Ryuji Kohno ,  Tetsuo Kumazawa ,  Makoto Kitano ,  Akihiko Ariga ,  Yuji Wada ,  Naoto Ban ,  Shuji Shibuya ,  Yasuhiro Motoyama ,  Kunio Matsumoto ,  Susumu Kasukabe ,  Terutaka Mori ,  Hidetaka Shigi ,  Takayoshi Watanabe

IPC分类号： G01R3126

CPC分类号： G01R3/00 ,  G01R1/0735

摘要： Dispersion of a load may be kept within a predetermined allowance even when a plurality of probes in a large area are pressed in batch by pressing the probes provided in a membrane against a wafer by applying a pressure load to a plurality of places on a plane of the pressure members on the side opposite the wafer in a probe test step, burn-in test step which represent typical semiconductor device manufacturing steps. It is then possible to provide semiconductor devices and a manufacturing method thereof which enhance the reliability and productivity of the semiconductor devices by probing a large number of integrated circuits or a large size integrated circuit at the same time.

摘要翻译： 即使当大量区域中的多个探针通过将设置在膜中的探针压在晶片上时，通过将压力负载施加到多个位置的平面上的多个位置，负载的分散也可以保持在预定容限内 在探针测试步骤中与晶片相对的一侧的压力构件，代表典型的半导体器件制造步骤的老化测试步骤。 因此，可以提供通过同时探测大量集成电路或大尺寸集成电路来提高半导体器件的可靠性和生产率的半导体器件及其制造方法。

公开(公告)号：US06864568B2

公开(公告)日：2005-03-08

申请号：US10252546

申请日：2002-09-24

申请人： Ryuji Kohno ,  Hiroya Shimizu ,  Masatoshi Kanamaru ,  Atsushi Hosogane ,  Toshio Miyatake ,  Hideo Miura ,  Tatsuya Nagata ,  Yoshishige Endo ,  Masaaki Namba ,  Yuji Wada

发明人： Ryuji Kohno ,  Hiroya Shimizu ,  Masatoshi Kanamaru ,  Atsushi Hosogane ,  Toshio Miyatake ,  Hideo Miura ,  Tatsuya Nagata ,  Yoshishige Endo ,  Masaaki Namba ,  Yuji Wada

IPC分类号： G01R31/26 ,  G01R1/04 ,  G01R1/073 ,  H01L21/66 ,  H01L23/02

CPC分类号： G01R1/0483 ,  H01L2924/0002 ,  H01L2924/00

摘要： A packaging device for holding thereon a plurality of semiconductor devices to be inspected on an inspection device including a probe to be electrically connected to an electrode of each of the semiconductor devices, comprises, holes for respectively receiving detachably therein the semiconductor devices to keep a positional relationship among the semiconductor devices and a positional relationship between the packaging device and each of the semiconductor devices constant with a spacing between the semiconductor devices, in a direction perpendicular to a thickness direction of the semiconductor devices, and electrically conductive members adapted to be connected respectively to the electrodes of the semiconductor devices, and extending to an exterior of the packaging device so that the probe is connected to each of the electrically conductive members.

摘要翻译： 一种用于在其上保持要检查的多个待检查的半导体器件的封装装置，包括：电连接到每个半导体器件的电极的探针，包括：用于分别接收半导体器件中的可分离地接收的孔，以保持位置 半导体器件之间的关系以及在与半导体器件的厚度方向垂直的方向上半导体器件之间的间隔恒定的封装器件和每个半导体器件之间的位置关系以及适于分别连接的导电部件 并且延伸到包装装置的外部，使得探针连接到每个导电构件。

公开(公告)号：US06465264B1

公开(公告)日：2002-10-15

申请号：US09654612

申请日：2000-09-01

申请人： Ryuji Kohno ,  Hiroya Shimizu ,  Masatoshi Kanamaru ,  Atsushi Hosogane ,  Toshio Miyatake ,  Hideo Miura ,  Tatsuya Nagata ,  Yoshishige Endo ,  Masaaki Namba ,  Yuji Wada

发明人： Ryuji Kohno ,  Hiroya Shimizu ,  Masatoshi Kanamaru ,  Atsushi Hosogane ,  Toshio Miyatake ,  Hideo Miura ,  Tatsuya Nagata ,  Yoshishige Endo ,  Masaaki Namba ,  Yuji Wada

IPC分类号： G01R3126

CPC分类号： G01R1/0483 ,  H01L2924/0002 ,  H01L2924/00

摘要： A packaging device for holding thereon a plurality of semiconductor devices to be inspected on an inspection device including a probe to be electrically connected to an electrode of each of the semiconductor devices, comprises, holes for respectively receiving detachably therein the semiconductor devices to keep a positional relationship among the semiconductor devices and a positional relationship between the packaging device and each of the semiconductor devices constant with a spacing between the semiconductor devices, in a direction perpendicular to a thickness direction of the semiconductor devices, and electrically conductive members adapted to be connected respectively to the electrodes of the semiconductor devices, and extending to an exterior of the packaging device so that the probe is connected to each of the electrically conductive members.

摘要翻译： 一种用于在其上保持要检查的多个待检查的半导体器件的封装装置，包括：电连接到每个半导体器件的电极的探针，包括：用于分别接收半导体器件中的可分离地接收的孔，以保持位置 半导体器件之间的关系以及在与半导体器件的厚度方向垂直的方向上半导体器件之间的间隔恒定的封装器件和每个半导体器件之间的位置关系以及适于分别连接的导电部件 并且延伸到包装装置的外部，使得探针连接到每个导电构件。

公开(公告)号：US06774654B2

公开(公告)日：2004-08-10

申请号：US10316828

申请日：2002-12-12

申请人： Masatoshi Kanamaru ,  Yoshishige Endo ,  Takanorr Aono ,  Ryuji Kohno ,  Toshio Miyatake ,  Hideyuki Aoki ,  Naoto Ban

发明人： Masatoshi Kanamaru ,  Yoshishige Endo ,  Takanorr Aono ,  Ryuji Kohno ,  Toshio Miyatake ,  Hideyuki Aoki ,  Naoto Ban

IPC分类号： G01R3102

CPC分类号： G01R1/07357 ,  Y10S977/874

摘要： A semiconductor inspecting apparatus having a plurality of electrical connection boards arranged in the inspecting apparatus and a plurality of probes respectively provided on a plurality of beams formed on a first board of said plurality of electrical connection boards, the probes being adapted to be individually brought into contact with a plurality of electrode pads of a semiconductor device for inspection, so as to inspect the semiconductor device while establishing electrical connection therebetween. A one-end supported beam is used as each of the beams, and each of the probes is formed at a portion shifted in a rectangular direction to a center line of a longitudinal direction of the one-end supported beam.

摘要翻译： 一种具有布置在检查装置中的多个电连接板和分别设置在形成在所述多个电连接板的第一板上的多个梁上的多个探针的半导体检查装置，所述探针适于单独地进入 与用于检查的半导体器件的多个电极焊盘接触，以便在其间建立电连接的同时检查半导体器件。 使用一端支撑梁作为每个梁，并且每个探针形成在沿着矩形方向偏移到一端支撑梁的纵向方向的中心线的部分。

公开(公告)号：US06714030B2

公开(公告)日：2004-03-30

申请号：US10390412

申请日：2003-03-18

申请人： Ryuji Kohno ,  Hideo Miura ,  Yoshishige Endo ,  Masatoshi Kanamaru ,  Atsushi Hosogane ,  Hideyuki Aoki ,  Naoto Ban

发明人： Ryuji Kohno ,  Hideo Miura ,  Yoshishige Endo ,  Masatoshi Kanamaru ,  Atsushi Hosogane ,  Hideyuki Aoki ,  Naoto Ban

IPC分类号： G01R3102

CPC分类号： H01L22/32 ,  G01R1/06711 ,  G01R1/06738 ,  G01R1/07314 ,  G01R3/00 ,  H01L23/13 ,  H01L2924/0002 ,  H01L2924/13091 ,  H01L2924/00

摘要： A semiconductor inspection apparatus which is possible to inspect a plurality of semiconductor devices collectively at one time, which has conventionally been difficult because of precision or the like of probes. A method of manufacturing the semiconductor inspection apparatus comprises the steps of forming a cover film on a surface of the silicon substrate and forming a plurality of probes of a polygonal cone shape or a circular cone shape through etching after patterning by photolithography, after the cover film is removed, again forming a cover film on the surface of the silicon substrate and forming a beam or a diaphragm for each probe through etching after patterning by photolithography, after the cover film is removed, again forming a cover film on the surface of the silicon substrate and forming a through hole corresponding to the probe through etching after patterning by photolithography, and after the cover film is removed, forming an insulating film on the surface of the silicon substrate, forming a metal film on a surface of the insulating film, and forming a wiring lead through etching after patterning by photolithography.

摘要翻译： 可以一次共同地检查多个半导体器件的半导体检查装置，由于探针的精度等，以前难以进行。 一种制造半导体检查装置的方法包括以下步骤：在硅衬底的表面上形成覆盖膜，并通过光刻图案化之后通过蚀刻形成多个锥形或圆锥形的多个探针， 被去除，再次在硅衬底的表面上形成覆盖膜，并且通过光刻在图案化之后通过蚀刻形成用于每个探针的光束或隔膜，在除去覆盖膜之后，再次在硅表面上形成覆盖膜 在通过光刻图案化之后通过蚀刻形成与探针对应的通孔，并且在除去覆盖膜之后，在硅衬底的表面上形成绝缘膜，在绝缘膜的表面上形成金属膜，以及 通过光刻在图案化之后通过蚀刻形成布线引线。

公开(公告)号：US06548315B2

公开(公告)日：2003-04-15

申请号：US10057921

申请日：2002-01-29

申请人： Ryuji Kohno ,  Hideo Miura ,  Yoshishige Endo ,  Masatoshi Kanamaru ,  Atsushi Hosogane ,  Hideyuki Aoki ,  Naoto Ban

发明人： Ryuji Kohno ,  Hideo Miura ,  Yoshishige Endo ,  Masatoshi Kanamaru ,  Atsushi Hosogane ,  Hideyuki Aoki ,  Naoto Ban

IPC分类号： H01L2166

CPC分类号： H01L22/32 ,  G01R1/06711 ,  G01R1/06738 ,  G01R1/07314 ,  G01R3/00 ,  H01L23/13 ,  H01L2924/0002 ,  H01L2924/13091 ,  H01L2924/00

摘要： A semiconductor inspection apparatus which is possible to inspect a plurality of semiconductor devices collectively at one time, which has conventionally been difficult because of precision or the like of probes. A method of manufacturing the semiconductor inspection apparatus comprises the steps of forming a cover film on a surface of the silicon substrate and forming a plurality of probes of a polygonal cone shape or a circular cone shape through etching after patterning by photolithography, after the cover film is removed, again forming a cover film on the surface of the silicon substrate and forming a beam or a diaphragm for each probe through etching after patterning by photolithography, after the cover film is removed, again forming a cover film on the surface of the silicon substrate and forming a through hole corresponding to the probe through etching after patterning by photolithography, and after the cover film is removed, forming an insulating film on the surface of the silicon substrate, forming a metal film on a surface of the insulating film, and forming a wiring lead through etching after patterning by photolithography.