公开(公告)号：US06455335B1

公开(公告)日：2002-09-24

申请号：US09653624

申请日：2000-08-31

申请人： Ryuji Kohno ,  Tetsuo Kumazawa ,  Makoto Kitano ,  Akihiko Ariga ,  Yuji Wada ,  Naoto Ban ,  Shuji Shibuya ,  Yasuhiro Motoyama ,  Kunio Matsumoto ,  Susumu Kasukabe ,  Terutaka Mori ,  Hidetaka Shigi ,  Takayoshi Watanabe

发明人： Ryuji Kohno ,  Tetsuo Kumazawa ,  Makoto Kitano ,  Akihiko Ariga ,  Yuji Wada ,  Naoto Ban ,  Shuji Shibuya ,  Yasuhiro Motoyama ,  Kunio Matsumoto ,  Susumu Kasukabe ,  Terutaka Mori ,  Hidetaka Shigi ,  Takayoshi Watanabe

IPC分类号： G01R3126

CPC分类号： G01R3/00 ,  G01R1/0735

摘要： Dispersion of load may be kept within an allowance even when a plurality of probes in a large area are pressed in batch by pressing the probes provided in a membrane to a wafer by applying a pressure load to a plurality of places of a plane of pressure members on the side opposite from the wafer in a probe test step/burn-in test step which is one of semiconductor device manufacturing steps. It is then possible to provide semiconductor devices and a manufacturing method thereof which enhance the reliability and productivity of the semiconductor devices by probing a large number of integrated circuits or a large size integrated circuit in the same time.

公开(公告)号：US06197603B1

公开(公告)日：2001-03-06

申请号：US09157153

申请日：1998-09-18

申请人： Ryuji Kohno ,  Tetsuo Kumazawa ,  Makoto Kitano ,  Akihiko Ariga ,  Yuji Wada ,  Naoto Ban ,  Shuji Shibuya ,  Yasuhiro Motoyama ,  Kunio Matsumoto ,  Susumu Kasukabe ,  Terutaka Mori ,  Hidetaka Shigi ,  Takayoshi Watanabe

发明人： Ryuji Kohno ,  Tetsuo Kumazawa ,  Makoto Kitano ,  Akihiko Ariga ,  Yuji Wada ,  Naoto Ban ,  Shuji Shibuya ,  Yasuhiro Motoyama ,  Kunio Matsumoto ,  Susumu Kasukabe ,  Terutaka Mori ,  Hidetaka Shigi ,  Takayoshi Watanabe

IPC分类号： G01R3126

CPC分类号： G01R3/00 ,  G01R1/0735

摘要： Dispersion of a load may be kept within a predetermined allowance even when a plurality of probes in a large area are pressed in batch by pressing the probes provided in a membrane against a wafer by applying a pressure load to a plurality of places on a plane of the pressure members on the side opposite the wafer in a probe test step, burn-in test step which represent typical semiconductor device manufacturing steps. It is then possible to provide semiconductor devices and a manufacturing method thereof which enhance the reliability and productivity of the semiconductor devices by probing a large number of integrated circuits or a large size integrated circuit at the same time.

摘要翻译： 即使当大量区域中的多个探针通过将设置在膜中的探针压在晶片上时，通过将压力负载施加到多个位置的平面上的多个位置，负载的分散也可以保持在预定容限内 在探针测试步骤中与晶片相对的一侧的压力构件，代表典型的半导体器件制造步骤的老化测试步骤。 因此，可以提供通过同时探测大量集成电路或大尺寸集成电路来提高半导体器件的可靠性和生产率的半导体器件及其制造方法。

公开(公告)号：US07198962B2

公开(公告)日：2007-04-03

申请号：US10411283

申请日：2003-04-11

申请人： Ryuji Kohno ,  Tetsuo Kumazawa ,  Makoto Kitano ,  Akihiko Ariga ,  Yuji Wada ,  Naoto Ban ,  Shuji Shibuya ,  Yasuhiro Motoyama ,  Kunio Matsumoto ,  Susumu Kasukabe ,  Terutaka Mori ,  Hidetaka Shigi ,  Takayoshi Watanabe

发明人： Ryuji Kohno ,  Tetsuo Kumazawa ,  Makoto Kitano ,  Akihiko Ariga ,  Yuji Wada ,  Naoto Ban ,  Shuji Shibuya ,  Yasuhiro Motoyama ,  Kunio Matsumoto ,  Susumu Kasukabe ,  Terutaka Mori ,  Hidetaka Shigi ,  Takayoshi Watanabe

IPC分类号： G01R31/26 ,  H01L21/66 ,  H01L21/00 ,  H01L21/48

CPC分类号： G01R3/00 ,  G01R1/0735

摘要： Dispersion of load may be kept within an allowance even when a plurality of probes in a large area are pressed in batch by pressing the probes provided in a membrane to a wafer by applying a pressure load to a plurality of places of a plane of pressure members on the side opposite from the wafer in a probe test step/burn-in test step which is one of semiconductor device manufacturing steps. It is then possible to provide semiconductor devices and a manufacturing method thereof which enhance the reliability and productivity of the semiconductor devices by probing a large number of integrated circuits or a large size integrated circuit in the same time.

摘要翻译： 即使当大量区域中的多个探针通过将设置在膜中的探针压迫到晶片而将压力负载施加到压力构件的平面的多个位置时，负载的分散也可以保持在容许范围内 在作为半导体器件制造步骤之一的探针测试步骤/老化测试步骤中与晶片相对的一侧。 因此，可以提供通过同时探测大量集成电路或大尺寸集成电路来提高半导体器件的可靠性和生产率的半导体器件及其制造方法。

公开(公告)号：US06566150B2

公开(公告)日：2003-05-20

申请号：US10171695

申请日：2002-06-17

申请人： Ryuji Kohno ,  Tetsuo Kumazawa ,  Makoto Kitano ,  Akihiko Ariga ,  Yuji Wada ,  Naoto Ban ,  Shuji Shibuya ,  Yasuhiro Motoyama ,  Kunio Matsumoto ,  Susumu Kasukabe ,  Terutaka Mori ,  Hidetaka Shigi ,  Takayoshi Watanabe

发明人： Ryuji Kohno ,  Tetsuo Kumazawa ,  Makoto Kitano ,  Akihiko Ariga ,  Yuji Wada ,  Naoto Ban ,  Shuji Shibuya ,  Yasuhiro Motoyama ,  Kunio Matsumoto ,  Susumu Kasukabe ,  Terutaka Mori ,  Hidetaka Shigi ,  Takayoshi Watanabe

IPC分类号： G01R3126

CPC分类号： G01R3/00 ,  G01R1/0735

摘要： Dispersion of load may be kept within an allowance even when a plurality of probes in a large area are pressed in batch by pressing the probes provided in a membrane to a wafer by applying a pressure load to a plurality of places of a plane of pressure members on the side opposite from the wafer in a probe test step/burn-in test step which is one of semiconductor device manufacturing steps. It is then possible to provide semiconductor devices and a manufacturing method thereof which enhance the reliability and productivity of the semiconductor devices by probing a large number of integrated circuits or a large size integrated circuit in the same time.

公开(公告)号：US07219422B2

公开(公告)日：2007-05-22

申请号：US10765917

申请日：2004-01-29

申请人： Yuji Wada ,  Susumu Kasukabe ,  Takehiko Hasebe ,  Yasunori Narizuka ,  Akira Yabushita ,  Terutaka Mori ,  Akio Hasebe ,  Yasuhiro Motoyama ,  Teruo Shoji ,  Masakazu Sueyoshi

发明人： Yuji Wada ,  Susumu Kasukabe ,  Takehiko Hasebe ,  Yasunori Narizuka ,  Akira Yabushita ,  Terutaka Mori ,  Akio Hasebe ,  Yasuhiro Motoyama ,  Teruo Shoji ,  Masakazu Sueyoshi

IPC分类号： H05K3/00 ,  H01R9/00

CPC分类号： G01R1/07314 ,  G01R31/2872 ,  Y10T29/41 ,  Y10T29/49128 ,  Y10T29/49147 ,  Y10T29/49155 ,  Y10T29/49169 ,  Y10T29/49798

摘要： The fabrication of a semiconductor integrated circuit device involves testing using a pushing mechanism that is constructed by forming, over the upper surface of a thin film probe, a reinforcing material having a linear expansion coefficient (thermal expansion coefficient) almost equal to that of a wafer to be tested; forming a groove in the reinforcing material above a contact terminal; placing an elastomer in the groove so that a predetermined amount projects out of the groove; and disposing a pusher and another elastomer to sandwich the pusher between the elastomers. With the use of such a probe, it is possible to improve the throughput of wafer-level electrical testing of a semiconductor integrated circuit.

摘要翻译： 半导体集成电路器件的制造包括使用推压机构进行测试，所述推压机构通过在薄膜探针的上表面上形成具有几乎等于晶片的线性膨胀系数（热膨胀系数）的增强材料而构成 待测 在接触端子上方的增强材料中形成凹槽; 将弹性体放置在所述槽中，使得预定量突出到所述凹槽中; 并且设置推进器和另一种弹性体以将推进器夹在弹性体之间。 通过使用这样的探针，可以提高半导体集成电路的晶片级电气测试的吞吐量。

公开(公告)号：US07351597B2

公开(公告)日：2008-04-01

申请号：US11750371

申请日：2007-05-18

申请人： Yuji Wada ,  Susumu Kasukabe ,  Takehiko Hasebe ,  Yasunori Narizuka ,  Akira Yabushita ,  Terutaka Mori ,  Akio Hasebe ,  Yasuhiro Motoyama ,  Teruo Shoji ,  Masakazu Sueyoshi

发明人： Yuji Wada ,  Susumu Kasukabe ,  Takehiko Hasebe ,  Yasunori Narizuka ,  Akira Yabushita ,  Terutaka Mori ,  Akio Hasebe ,  Yasuhiro Motoyama ,  Teruo Shoji ,  Masakazu Sueyoshi

IPC分类号： H01L21/66

CPC分类号： G01R1/07314 ,  G01R31/2872 ,  Y10T29/41 ,  Y10T29/49128 ,  Y10T29/49147 ,  Y10T29/49155 ,  Y10T29/49169 ,  Y10T29/49798

摘要： The fabrication of a semiconductor integrated circuit device involves testing using a pushing mechanism that is constructed by forming, over the upper surface of a thin film probe, a reinforcing material having a linear expansion coefficient (thermal expansion coefficient) almost equal to that of a wafer to be tested; forming a groove in the reinforcing material above a contact terminal; placing an elastomer in the groove so that a predetermined amount projects out of the groove; and disposing a pusher and another elastomer to sandwich the pusher between the elastomers. With the use of such a probe, it is possible to improve the throughput of wafer-level electrical testing of a semiconductor integrated circuit.

摘要翻译： 半导体集成电路器件的制造包括使用推压机构进行测试，所述推压机构通过在薄膜探针的上表面上形成具有几乎等于晶片的线性膨胀系数（热膨胀系数）的增强材料而构成 待测 在接触端子上方的增强材料中形成凹槽; 将弹性体放置在所述槽中，使得预定量突出到所述凹槽中; 并且设置推进器和另一种弹性体以将推进器夹在弹性体之间。 通过使用这样的探针，可以提高半导体集成电路的晶片级电气测试的吞吐量。

公开(公告)号：US20070218572A1

公开(公告)日：2007-09-20

申请号：US11750371

申请日：2007-05-18

申请人： Yuji Wada ,  Susumu Kasukabe ,  Takehiko Hasebe ,  Yasunori Narizuka ,  Akira Yabushita ,  Terutaka Mori ,  Akio Hasebe ,  Yasuhiro Motoyama ,  Teruo Shoji ,  Masakazu Sueyoshi

发明人： Yuji Wada ,  Susumu Kasukabe ,  Takehiko Hasebe ,  Yasunori Narizuka ,  Akira Yabushita ,  Terutaka Mori ,  Akio Hasebe ,  Yasuhiro Motoyama ,  Teruo Shoji ,  Masakazu Sueyoshi

IPC分类号： H01L21/66

CPC分类号： G01R1/07314 ,  G01R31/2872 ,  Y10T29/41 ,  Y10T29/49128 ,  Y10T29/49147 ,  Y10T29/49155 ,  Y10T29/49169 ,  Y10T29/49798

摘要： The fabrication of a semiconductor integrated circuit device involves testing using a pushing mechanism that is constructed by forming, over the upper surface of a thin film probe, a reinforcing material having a linear expansion coefficient (thermal expansion coefficient) almost equal to that of a wafer to be tested; forming a groove in the reinforcing material above a contact terminal; placing an elastomer in the groove so that a predetermined amount projects out of the groove; and disposing a pusher and another elastomer to sandwich the pusher between the elastomers. With the use of such a probe, it is possible to improve the throughput of wafer-level electrical testing of a semiconductor integrated circuit.

摘要翻译： 半导体集成电路器件的制造包括使用推压机构进行测试，所述推压机构通过在薄膜探针的上表面上形成具有几乎等于晶片的线性膨胀系数（热膨胀系数）的增强材料而构成 待测 在接触端子上方的增强材料中形成凹槽; 将弹性体放置在所述槽中，使得预定量突出到所述凹槽中; 并且设置推进器和另一种弹性体以将推进器夹在弹性体之间。 通过使用这样的探针，可以提高半导体集成电路的晶片级电气测试的吞吐量。

公开(公告)号：US06696849B2

公开(公告)日：2004-02-24

申请号：US09964708

申请日：2001-09-28

申请人： Naoto Ban ,  Masaaki Namba ,  Akio Hasebe ,  Yuji Wada ,  Ryuji Kohno ,  Akira Seito ,  Yasuhiro Motoyama

发明人： Naoto Ban ,  Masaaki Namba ,  Akio Hasebe ,  Yuji Wada ,  Ryuji Kohno ,  Akira Seito ,  Yasuhiro Motoyama

IPC分类号： G01R3102

CPC分类号： G01R31/2831

摘要： A testing apparatus and a fabricating method of a semiconductor integrated circuit device for reducing the fabrication cost by placing, in the wafer level burn-in, divided contactors in equally contact with the full surface of wafer, enabling repair of each contactor and improving the yield of contactors. The cassette structure of the mechanical pressurizing system in the testing apparatus is structured with a plurality of divided silicon contactor blocks and a guide frame for integrating these blocks and employs the wafer full surface simultaneous contact system of the divided contactor integration type. Each probe of the silicon contactor is equally placed in contact in the predetermined pressure with each test pad of each chip of the test wafer by mechanically pressuring each silicon contactor block which moves individually, the test control signal is supplied to each chip and this test result signal is obtained for the wafer level burn-in test.

摘要翻译： 一种半导体集成电路器件的测试装置和制造方法，用于通过在晶片级老化中放置与晶片的整个表面均匀接触的分割的接触器来降低制造成本，从而能够修复每个接触器并提高产量 的接触器。 测试装置中的机械加压系统的盒式结构由多个分开的硅接触器块和用于集成这些块的引导框架构成，并且采用分开的接触器一体化型的晶片全表面同时接触系统。 硅接触器的每个探针通过机械加压每个单独移动的硅接触器块，将测试控制信号提供给每个芯片，并且测试结果与测试晶片的每个芯片的每个测试焊盘等同地以预定压力接触 获得晶片级老化测试信号。

公开(公告)号：US06864568B2

公开(公告)日：2005-03-08

申请号：US10252546

申请日：2002-09-24

申请人： Ryuji Kohno ,  Hiroya Shimizu ,  Masatoshi Kanamaru ,  Atsushi Hosogane ,  Toshio Miyatake ,  Hideo Miura ,  Tatsuya Nagata ,  Yoshishige Endo ,  Masaaki Namba ,  Yuji Wada

发明人： Ryuji Kohno ,  Hiroya Shimizu ,  Masatoshi Kanamaru ,  Atsushi Hosogane ,  Toshio Miyatake ,  Hideo Miura ,  Tatsuya Nagata ,  Yoshishige Endo ,  Masaaki Namba ,  Yuji Wada

IPC分类号： G01R31/26 ,  G01R1/04 ,  G01R1/073 ,  H01L21/66 ,  H01L23/02

CPC分类号： G01R1/0483 ,  H01L2924/0002 ,  H01L2924/00

摘要： A packaging device for holding thereon a plurality of semiconductor devices to be inspected on an inspection device including a probe to be electrically connected to an electrode of each of the semiconductor devices, comprises, holes for respectively receiving detachably therein the semiconductor devices to keep a positional relationship among the semiconductor devices and a positional relationship between the packaging device and each of the semiconductor devices constant with a spacing between the semiconductor devices, in a direction perpendicular to a thickness direction of the semiconductor devices, and electrically conductive members adapted to be connected respectively to the electrodes of the semiconductor devices, and extending to an exterior of the packaging device so that the probe is connected to each of the electrically conductive members.

摘要翻译： 一种用于在其上保持要检查的多个待检查的半导体器件的封装装置，包括：电连接到每个半导体器件的电极的探针，包括：用于分别接收半导体器件中的可分离地接收的孔，以保持位置 半导体器件之间的关系以及在与半导体器件的厚度方向垂直的方向上半导体器件之间的间隔恒定的封装器件和每个半导体器件之间的位置关系以及适于分别连接的导电部件 并且延伸到包装装置的外部，使得探针连接到每个导电构件。

公开(公告)号：US06465264B1

公开(公告)日：2002-10-15

申请号：US09654612

申请日：2000-09-01

申请人： Ryuji Kohno ,  Hiroya Shimizu ,  Masatoshi Kanamaru ,  Atsushi Hosogane ,  Toshio Miyatake ,  Hideo Miura ,  Tatsuya Nagata ,  Yoshishige Endo ,  Masaaki Namba ,  Yuji Wada

发明人： Ryuji Kohno ,  Hiroya Shimizu ,  Masatoshi Kanamaru ,  Atsushi Hosogane ,  Toshio Miyatake ,  Hideo Miura ,  Tatsuya Nagata ,  Yoshishige Endo ,  Masaaki Namba ,  Yuji Wada

IPC分类号： G01R3126

CPC分类号： G01R1/0483 ,  H01L2924/0002 ,  H01L2924/00

摘要： A packaging device for holding thereon a plurality of semiconductor devices to be inspected on an inspection device including a probe to be electrically connected to an electrode of each of the semiconductor devices, comprises, holes for respectively receiving detachably therein the semiconductor devices to keep a positional relationship among the semiconductor devices and a positional relationship between the packaging device and each of the semiconductor devices constant with a spacing between the semiconductor devices, in a direction perpendicular to a thickness direction of the semiconductor devices, and electrically conductive members adapted to be connected respectively to the electrodes of the semiconductor devices, and extending to an exterior of the packaging device so that the probe is connected to each of the electrically conductive members.

摘要翻译： 一种用于在其上保持要检查的多个待检查的半导体器件的封装装置，包括：电连接到每个半导体器件的电极的探针，包括：用于分别接收半导体器件中的可分离地接收的孔，以保持位置 半导体器件之间的关系以及在与半导体器件的厚度方向垂直的方向上半导体器件之间的间隔恒定的封装器件和每个半导体器件之间的位置关系以及适于分别连接的导电部件 并且延伸到包装装置的外部，使得探针连接到每个导电构件。