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    Semiconductor wafer and semiconductor device
    2.
    发明授权
    Semiconductor wafer and semiconductor device 有权
    半导体晶圆和半导体器件

    公开(公告)号：US06329700B1

    公开(公告)日：2001-12-11

    申请号：US09253041

    申请日：1999-02-19

    申请人： Youichi Ishimura ,  Hideki Takahashi ,  Norihisa Asano

    发明人： Youichi Ishimura ,  Hideki Takahashi ,  Norihisa Asano

    IPC分类号： H01L23544

    CPC分类号： H01L21/78

    摘要： A semiconductor wafer and a semiconductor device with more chips are obtained. The semiconductor wafer includes a plurality of dicing lines (DXa, DXb, DYa, DYb) extending in the lateral direction (X) and in the longitudinal direction (Y) with an interval (L1) therebetween, and a semiconductor element forming region (CR1) with a semiconductor element, sectioned by the dicing lines (DXa, DXb, DYa, DYb). The dicing lines both in the lateral direction (X) and in the longitudinal direction (Y) have alternate widths (La, Lb), one of which (Lb) is larger than the other (La).

    摘要翻译： 获得具有更多芯片的半导体晶片和半导体器件。 半导体晶片包括沿横向（X）和纵向方向（Y）以它们之间的间隔（L1）延伸的多个切割线（DXa，DXb，DYa，DYb）和半导体元件形成区域（CR1 ）具有由切割线（DXa，DXb，DYa，DYb）分割的半导体元件。 在横向（X）和纵向（Y）上的切割线都具有交替的宽度（La，Lb），其中一个（Lb）大于另一个（La）。

    Selective recrystallization of semiconductor
    3.
    发明授权
    Selective recrystallization of semiconductor 有权
    半导体选择性重结晶

    公开(公告)号：US08466048B2

    公开(公告)日：2013-06-18

    申请号：US13256050

    申请日：2010-03-09

    申请人： Yoshiyuki Itoh ,  Masashi Maekawa ,  Norihisa Asano ,  Hiroki Taniyama

    发明人： Yoshiyuki Itoh ,  Masashi Maekawa ,  Norihisa Asano ,  Hiroki Taniyama

    IPC分类号： H01L21/20

    CPC分类号： H01L29/861 ,  G02F2001/13312 ,  H01L21/02422 ,  H01L21/02491 ,  H01L21/02494 ,  H01L21/02532 ,  H01L21/02672 ,  H01L21/02675 ,  H01L27/12 ,  H01L27/1229 ,  H01L27/1285

    摘要： Disclosed is a semiconductor device which includes a substrate 11, a thin film transistor 20 having a first semiconductor layer 16A that is supported by the substrate 11, a thin film diode 30 having a second semiconductor layer 16B that is supported by the substrate 11, and a metal layer 12 that is formed between the substrate 11 and the second semiconductor layer 16B. The first semiconductor layer 16A is a laterally grown crystalline semiconductor film, and the second semiconductor layer 16B is a crystalline semiconductor film that contains fine crystal grains. The average surface roughness of the second semiconductor layer 16B is higher than the average surface roughness of the first semiconductor layer 16A. Consequently, the optical sensitivity of the TFD is improved and the reliability of the TFT is improved, as compared with those in the conventional semiconductor devices.

    摘要翻译： 公开了一种半导体器件，其包括基板11，具有由基板11支撑的第一半导体层16A的薄膜晶体管20，具有由基板11支撑的第二半导体层16B的薄膜二极管30，以及 形成在基板11和第二半导体层16B之间的金属层12。 第一半导体层16A是横向生长的晶体半导体膜，第二半导体层16B是含有细晶粒的结晶半导体膜。 第二半导体层16B的平均表面粗糙度高于第一半导体层16A的平均表面粗糙度。 因此，与以往的半导体装置相比，提高了TFD的光学灵敏度，提高了TFT的可靠性。

    SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME
    4.
    发明申请
    SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME 有权
    半导体器件及其制造方法

    公开(公告)号：US20110315995A1

    公开(公告)日：2011-12-29

    申请号：US13256050

    申请日：2010-03-09

    申请人： Yoshiyuki Itoh ,  Masashi Maekawa ,  Norihisa Asano ,  Hiroki Taniyama

    发明人： Yoshiyuki Itoh ,  Masashi Maekawa ,  Norihisa Asano ,  Hiroki Taniyama

    IPC分类号： H01L29/04 ,  H01L21/20

    CPC分类号： H01L29/861 ,  G02F2001/13312 ,  H01L21/02422 ,  H01L21/02491 ,  H01L21/02494 ,  H01L21/02532 ,  H01L21/02672 ,  H01L21/02675 ,  H01L27/12 ,  H01L27/1229 ,  H01L27/1285

    摘要： Disclosed is a semiconductor device which includes a substrate 11, a thin film transistor 20 having a first semiconductor layer 16A that is supported by the substrate 11, a thin film diode 30 having a second semiconductor layer 16B that is supported by the substrate 11, and a metal layer 12 that is formed between the substrate 11 and the second semiconductor layer 16B. The first semiconductor layer 16A is a laterally grown crystalline semiconductor film, and the second semiconductor layer 16B is a crystalline semiconductor film that contains fine crystal grains. The average surface roughness of the second semiconductor layer 16B is higher than the average surface roughness of the first semiconductor layer 16A. Consequently, the optical sensitivity of the TFD is improved and the reliability of the TFT is improved, as compared with those in the conventional semiconductor devices.

    摘要翻译： 公开了一种半导体器件，其包括基板11，具有由基板11支撑的第一半导体层16A的薄膜晶体管20，具有由基板11支撑的第二半导体层16B的薄膜二极管30，以及 形成在基板11和第二半导体层16B之间的金属层12。 第一半导体层16A是横向生长的晶体半导体膜，第二半导体层16B是含有细晶粒的结晶半导体膜。 第二半导体层16B的平均表面粗糙度高于第一半导体层16A的平均表面粗糙度。 因此，与以往的半导体装置相比，提高了TFD的光学灵敏度，提高了TFT的可靠性。

    SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME
    7.
    发明申请
    SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME 有权
    半导体器件及其制造方法

    公开(公告)号：US20130087924A1

    公开(公告)日：2013-04-11

    申请号：US13704396

    申请日：2011-04-20

    申请人： Norihisa Asano ,  Kazuyoshi Imae

    发明人： Norihisa Asano ,  Kazuyoshi Imae

    IPC分类号： H01L23/522 ,  H01L21/768

    CPC分类号： H01L23/522 ,  G02F1/1368 ,  H01L21/76838 ,  H01L27/12 ,  H01L27/124 ,  H01L27/1248 ,  H01L29/78606 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Disclosed is a semiconductor device provided with: lower-layer wiring formed on a substrate, an interlayer insulating film covering the lower-layer wiring, and a first upper-layer wiring line (18b) and a second upper-layer wiring line (18c) arranged on the interlayer insulating film and intersecting with the lower-layer wiring, and a level-difference adjustment protrusion is provided between the first upper-layer wiring line (18b) and the second upper-layer wiring line (18c) adjacent to a side section of the lower-layer wiring.

    摘要翻译： 公开了一种半导体器件，其具有：形成在基板上的下层布线，覆盖下层布线的层间绝缘膜，以及第一上层布线（18b）和第二上层布线（18c） 布置在层间绝缘膜上并与下层布线相交，并且在第一上层布线（18b）和与侧面相邻的第二上层布线（18c）之间设置有电平差调节突起 部分下层接线。

    Process for manufacturing an active element array substrate
    8.
    发明授权
    Process for manufacturing an active element array substrate 失效
    用于制造有源元件阵列基板的工艺

    公开(公告)号：US06326129B1

    公开(公告)日：2001-12-04

    申请号：US09526570

    申请日：2000-03-16

    申请人： Takashi Hirose ,  Junji Boshita ,  Norihisa Asano

    发明人： Takashi Hirose ,  Junji Boshita ,  Norihisa Asano

    IPC分类号： G02F11343

    CPC分类号： G02F1/136227

    摘要： A process for manufacturing an active element array substrate, such as for a display panel in a liquid crystal display device. The process comprises exposing photosensitive resin to an irradiation light from the rear face of the substrate and to another irradiation light applied from the front face of the substrate. The irradiation light from the front face of the substrate exposes a region encompassing substantially all of the pixel electrode extending from over a portion of the drain electrode to near the source and gate electrodes. This enables selective exposure of the photosensitive resin to the light from the front face even if scratches or dust exist on the rear face of the substrate during exposure to the light from the rear face, thus increasing the manufacturing yield of such active element array substrates.

    摘要翻译： 一种有源元件阵列基板的制造方法，例如液晶显示装置中的显示面板。 该方法包括将感光树脂暴露于来自基板的背面的照射光和从基板的正面施加的另一照射光。 来自基板的前表面的照射光暴露了从漏电极的一部分延伸到源电极和栅电极附近的基本上全部的像素电极的区域。 即使在曝光于背面的光时，即使在基板的背面存在划痕或灰尘，也能够使感光性树脂选择性地曝光于来自前表面的光，从而提高了这种有源元件阵列基板的制造成品率。