公开(公告)号：US06354913B1

公开(公告)日：2002-03-12

申请号：US09214431

申请日：1999-01-06

申请人： Naoto Miyashita ,  Yoshihiro Minami ,  Kenji Doi ,  Jun Takayasu ,  Hiroyuki Kohno ,  Hiroshi Kato ,  Kazuhiko Hayashi

发明人： Naoto Miyashita ,  Yoshihiro Minami ,  Kenji Doi ,  Jun Takayasu ,  Hiroyuki Kohno ,  Hiroshi Kato ,  Kazuhiko Hayashi

IPC分类号： B24B100

CPC分类号： B24B37/24 ,  B24B37/0056 ,  B24B37/044 ,  B24D3/20 ,  B24D3/344 ,  C09G1/02 ,  H01L21/3212

摘要： A semiconductor wafer or a film formed thereon is polished by using a polishing agent comprising abrasive containing silica particles as the main component, water as a solvent, and a water-soluble cellulose, an alkali metal impurity content of the polishing agent being 5C ppm or less where the polishing agent contains C % by weight of the water-soluble cellulose, so as to flatten the semiconductor wafer without doing damage to the wafer or the film formed thereon and without bringing about a dishing problem in the polished surface.

摘要翻译： 通过使用包含二氧化硅颗粒作为主要成分的研磨剂，作为溶剂的水和水溶性纤维素，研磨剂的碱金属杂质含量为5ppm或以下，研磨半导体晶片或其上形成的膜 抛光剂含有C％（重量）的水溶性纤维素，以使得半导体晶片平坦化，而不会对晶片或其上形成的膜造成损害，而不会在抛光表面产生凹陷问题。

公开(公告)号：US06241581B1

公开(公告)日：2001-06-05

申请号：US09055944

申请日：1998-04-07

申请人： Naoto Miyashita ,  Yoshihiro Minami

发明人： Naoto Miyashita ,  Yoshihiro Minami

IPC分类号： B24B100

CPC分类号： B24B53/017 ,  B24B37/04

摘要： A dresser is used which makes it possible to simultaneously dress and condition the surface of a polishing pad deteriorated by polishing a semiconductor wafer in the CMP process. The dresser is a dresser comprised of a ceramic such as dressing SiC, SiN, alumina or silica. Use of this dresser enables to shorten the time of dressing/conditioning the deteriorated polishing pad.

公开(公告)号：US06716087B2

公开(公告)日：2004-04-06

申请号：US09839240

申请日：2001-04-23

申请人： Naoto Miyashita ,  Yoshihiro Minami

发明人： Naoto Miyashita ,  Yoshihiro Minami

IPC分类号： B24B100

CPC分类号： B24B53/017 ,  B24B37/04

摘要： A dresser is used which makes it possible to simultaneously dress and condition the surface of a polishing pad deteriorated by polishing a semiconductor wafer in the CMP process. The dresser is a dresser comprised of a ceramic such as dressing SiC, SiN, alumina or silica. Use of this dresser enables to shorten the time of dressing/conditioning the deteriorated polishing pad.

摘要翻译： 使用修整器，其使得可以通过在CMP工艺中抛光半导体晶片来同时修整和调节抛光垫的表面劣化的表面。 修整器是由诸如修整SiC，SiN，氧化铝或二氧化硅的陶瓷组成的修整器。 使用这种修整器可以缩短修整/调理劣化的抛光垫的时间。

公开(公告)号：US07154151B2

公开(公告)日：2006-12-26

申请号：US11015036

申请日：2004-12-20

申请人： Yoshihiro Minami

发明人： Yoshihiro Minami

IPC分类号： H01L23/62

CPC分类号： H01L27/0255 ,  H01L27/1203 ,  H01L29/7841 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device comprises a semiconductor substrate; an embedded insulating layer provided on the semiconductor substrate; a semiconductor layer provided on the embedded insulating layer; a transistor including a first conductivity type source layer formed within the semiconductor layer, a first conductivity type drain layer formed in the semiconductor layer, and a channel forming region between the source layer and the drain layer; and an embedded insulating layer protective diode including a second conductivity type first diffusion layer and a first conductivity type second diffusion layer, the first diffusion layer being at the same potential as a semiconductor substrate region immediately below the channel forming region, the second diffusion layer being provided adjacently to the first diffusion layer and electrically connected to at least one of the source layer, the drain layer and the channel forming region.

摘要翻译： 半导体器件包括半导体衬底; 设置在半导体基板上的嵌入式绝缘层; 设置在所述嵌入绝缘层上的半导体层; 包括形成在所述半导体层内的第一导电类型源极层，形成在所述半导体层中的第一导电类型漏极层和所述源极层与所述漏极层之间的沟道形成区域的晶体管; 以及包括第二导电型第一扩散层和第一导电型第二扩散层的嵌入式绝缘层保护二极管，所述第一扩散层与所述沟道形成区域正下方的半导体衬底区域处于相同的电位，所述第二扩散层为 与第一扩散层相邻并且电连接到源极层，漏极层和沟道形成区域中的至少一个。

公开(公告)号：US06906384B2

公开(公告)日：2005-06-14

申请号：US10096655

申请日：2002-03-14

申请人： Takashi Yamada ,  Tsutomu Sato ,  Shinichi Nitta ,  Hajime Nagano ,  Ichiro Mizushima ,  Hisato Oyamatsu ,  Yoshihiro Minami ,  Shinji Miyano ,  Osamu Fujii

发明人： Takashi Yamada ,  Tsutomu Sato ,  Shinichi Nitta ,  Hajime Nagano ,  Ichiro Mizushima ,  Hisato Oyamatsu ,  Yoshihiro Minami ,  Shinji Miyano ,  Osamu Fujii

IPC分类号： H01L21/76 ,  H01L21/762 ,  H01L21/764 ,  H01L21/8234 ,  H01L21/8242 ,  H01L21/84 ,  H01L27/08 ,  H01L27/088 ,  H01L27/10 ,  H01L27/108 ,  H01L27/12 ,  H01L29/786 ,  H01L27/01

CPC分类号： H01L27/10861 ,  H01L21/76243 ,  H01L21/823481 ,  H01L21/84 ,  H01L27/10873 ,  H01L27/10894 ,  H01L27/1203 ,  H01L29/78639

摘要： A semiconductor device includes first and second semiconductor layers and first and second MOS transistors. The first semiconductor layer is provided on and electrically connected to the semiconductor substrate. The second semiconductor layer is provided near the first semiconductor layer and formed above the semiconductor substrate via one of an insulating film and a cavity. The first and second MOS transistors are respectively provided on the first and second semiconductor layers, and each has a gate electrode arranged parallel to a boundary between the first and second semiconductor layers.

摘要翻译： 半导体器件包括第一和第二半导体层以及第一和第二MOS晶体管。 第一半导体层设置在半导体衬底上并与之电连接。 第二半导体层设置在第一半导体层附近，并且经由绝缘膜和空腔中的一个形成在半导体基板的上方。 第一和第二MOS晶体管分别设置在第一和第二半导体层上，并且各自具有平行于第一和第二半导体层之间的边界排列的栅电极。

公开(公告)号：US20080237681A1

公开(公告)日：2008-10-02

申请号：US12051053

申请日：2008-03-19

申请人： Yoshihiro Minami

发明人： Yoshihiro Minami

IPC分类号： H01L29/788 ,  H01L21/336

CPC分类号： H01L29/7841 ,  H01L27/108 ,  H01L27/10802 ,  H01L27/10897

摘要： This disclosure concerns a semiconductor device comprising: a bulk substrate; an insulation layer provided on the bulk substrate; a semiconductor layer containing an active area on which a semiconductor element is formed, and a dummy active area isolated from the active area and not formed with a semiconductor element thereon, the semiconductor layer being provided on the insulation layer; and a supporting unit provided beneath the dummy active area to reach the bulk substrate piercing through the insulation layer, the supporting unit supporting the dummy active area.

摘要翻译： 本公开涉及一种半导体器件，包括：体基板; 设置在本体基板上的绝缘层; 包含其上形成有半导体元件的有源区的半导体层和与有源区隔离而不在其上形成有半导体元件的虚设有源区，所述半导体层设置在所述绝缘层上; 以及支撑单元，其设置在所述虚拟有源区域下方以到达穿过所述绝缘层的所述主体基板，所述支撑单元支撑所述虚拟有效区域。

公开(公告)号：US20060113686A1

公开(公告)日：2006-06-01

申请号：US11041250

申请日：2005-01-25

申请人： Yoshihiro Minami

发明人： Yoshihiro Minami

IPC分类号： H01L31/109

CPC分类号： H01L27/108 ,  H01L27/10802 ,  H01L29/7841 ,  Y10S257/90

摘要： A semiconductor memory device includes: a semiconductor device base having an insulating substrate and a semiconductor layer overlying it; a cell array formed on the semiconductor device base with cell transistors disposed in such a manner that each of source and drain layers is shared by adjacent two cell transistors arranged in a direction, the cell transistor having an electrically floating channel body to store data defined by a carrier accumulation state of the channel body; and logic transistors formed on the semiconductor device base to constitute a peripheral circuit of said cell array, wherein at least a part of source and drain layers of each the cell transistor is formed with a thickness different from source and drain layers of the logic transistors.

摘要翻译： 半导体存储器件包括：半导体器件基底，具有绝缘基底和覆盖其上的半导体层; 形成在半导体器件基底上的单元阵列，其中单元晶体管以这样的方式设置，使得源极和漏极层中的每一个由在一个方向上排列的相邻的两个单元晶体管共享，该单元晶体管具有电浮动沟道体，以存储由 通道体的载体积聚状态; 以及形成在所述半导体器件基底上的逻辑晶体管，以构成所述单元阵列的外围电路，其中每个所述单元晶体管的源极和漏极层的至少一部分形成为具有与所述逻辑晶体管的源极和漏极层不同的厚度。

公开(公告)号：US06933590B2

公开(公告)日：2005-08-23

申请号：US10653093

申请日：2003-09-03

申请人： Takashi Yamada ,  Atsushi Azuma ,  Yoshihiro Minami ,  Hajime Nagano ,  Hiroaki Yamada ,  Tatsuya Ohguro ,  Kenji Kojima ,  Kazumi Inoh

发明人： Takashi Yamada ,  Atsushi Azuma ,  Yoshihiro Minami ,  Hajime Nagano ,  Hiroaki Yamada ,  Tatsuya Ohguro ,  Kenji Kojima ,  Kazumi Inoh

IPC分类号： H01L21/02 ,  H01L21/762 ,  H01L21/8242 ,  H01L21/84 ,  H01L23/52 ,  H01L27/02 ,  H01L27/108 ,  H01L27/12 ,  H01L29/06

CPC分类号： H01L27/10894 ,  H01L21/76281 ,  H01L21/76289 ,  H01L21/84 ,  H01L27/0218 ,  H01L27/10829 ,  H01L27/10897 ,  H01L27/1203 ,  H01L2924/0002 ,  H01L2924/00

摘要： A convex polycrystalline silicon film is formed on a handle wafer. A semiconductor layer is formed on the polycrystalline silicon film. The semiconductor is thinner on its areas in which the convex polycrystalline silicon film is formed and is thicker on its areas in which the convex polycrystalline silicon film is not formed. An opening is formed in each of those areas of an insulating film which are located under respective thick-film semiconductor areas of the semiconductor layer. The polycrystalline silicon film is formed in the openings to connect electrically the thick-film semiconductor areas and the handle wafer together.

摘要翻译： 在手柄晶片上形成凸多晶硅膜。 在多晶硅膜上形成半导体层。 半导体在其形成凸多晶硅膜的区域较薄，并且在其中未形成凸多晶硅膜的区域较厚。 在位于半导体层的各个厚膜半导体区域的绝缘膜的每个区域中形成开口。 在开口中形成多晶硅膜，以将厚膜半导体区域和处理晶片电连接在一起。

公开(公告)号：US07995369B2

公开(公告)日：2011-08-09

申请号：US12332595

申请日：2008-12-11

申请人： Yoshihiro Minami ,  Ryo Fukuda ,  Takeshi Hamamoto

发明人： Yoshihiro Minami ,  Ryo Fukuda ,  Takeshi Hamamoto

IPC分类号： G11C17/00

CPC分类号： H01L27/101 ,  H01L27/1021 ,  H01L27/112 ,  H01L27/1203

摘要： This disclosure concerns a semiconductor memory device including bit lines; word lines; semiconductor layers arranged to correspond to crosspoints of the bit lines and the word lines; bit line contacts connecting between a first surface region and the bit lines, the first surface region being a part of a surface region of the semiconductor layers directed to the word lines and the bit lines; and a word-line insulating film formed on a second surface region adjacent to the first surface region, the second surface region being a part of out of the surface region, the word-line insulating film electrically insulating the semiconductor layer and the word line, wherein the semiconductor layer, the word line and the word-line insulating film form a capacitor, and when a potential difference is given between the word line and the bit line, the word-line insulating film is broken in order to store data.

摘要翻译： 本公开涉及包括位线的半导体存储器件; 字线 布置成对应于位线和字线的交叉点的半导体层; 连接在第一表面区域和位线之间的位线触点，第一表面区域是半导体层指向字线和位线的表面区域的一部分; 以及形成在与所述第一表面区域相邻的第二表面区域上的字线绝缘膜，所述第二表面区域是所述表面区域之外的一部分，所述字线绝缘膜使所述半导体层和所述字线电绝缘， 其中半导体层，字线和字线绝缘膜形成电容器，并且当在字线和位线之间给出电位差时，字线绝缘膜被破坏以便存储数据。

公开(公告)号：US06951794B2

公开(公告)日：2005-10-04

申请号：US10798568

申请日：2004-03-12

申请人： Yoshihiro Minami

发明人： Yoshihiro Minami

IPC分类号： H01L21/822 ,  H01F17/00 ,  H01F41/04 ,  H01L21/02 ,  H01L27/04 ,  H01L27/08 ,  H01L21/20 ,  H01L23/053 ,  H01L23/12 ,  H01L29/00 ,  H01L29/40

CPC分类号： H01L28/10 ,  H01F17/0006 ,  H01F41/042 ,  H01F2017/0046 ,  H01L27/08

摘要： A spiral inductor comprising: a substrate; a protruding portion which is formed on the top face of the substrate and the top of which serves as a dummy element for controlling a chemical mechanical polishing process; and a conductive layer which is formed on the substrate so as to have a spiral shape and which serves as an induction element, wherein the protruding portion is formed in a region other than a region directly below the conductive layer.

摘要翻译： 一种螺旋电感器，包括：基板; 形成在所述基板的上表面上的突出部，其顶部作为用于控制化学机械研磨的哑元件; 以及导电层，其形成在所述基板上以具有螺旋形状并且用作感应元件，其中所述突出部分形成在除了所述导电层正下方的区域之外的区域中。